EP1S40B956C5 Altera, EP1S40B956C5 Datasheet - Page 443
EP1S40B956C5
Manufacturer Part Number
EP1S40B956C5
Description
IC STRATIX FPGA 40K LE 956-BGA
Manufacturer
Altera
Series
Stratix®r
Datasheet
1.EP1S10F484I6N.pdf
(864 pages)
Specifications of EP1S40B956C5
Number Of Logic Elements/cells
41250
Number Of Labs/clbs
4125
Total Ram Bits
3423744
Number Of I /o
683
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
956-BGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
EP1S40B956C5
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
- Current page: 443 of 864
- Download datasheet (11Mb)
High-Speed
Interfaces
Altera Corporation
June 2006
f
See the Stratix Device Family Data Sheet section in the Stratix Device
Handbook, Volume 1; the Stratix GX Device Family Data Sheet section of the
Stratix GX Device Handbook, Volume 1; and the High-Speed Differential I/O
Interfaces in Stratix Devices chapter for more information on differential
I/O standards.
In addition to current industry physical I/O standards, Stratix and
Stratix GX devices also support a variety of emerging high-speed
interfaces. This section provides an overview of these interfaces.
OIF-SPI4.2
This implementation agreement is widely used in the industry for
OC-192 and 10-Gbps multi-service system interfaces. SONET and SDH
are synchronous transmission systems over which data packets are
transferred. POS-PHY Level 4 is a standard interface for switches and
routers, and defines the operation between a physical layer (PHY) device
and link layer devices (ATM, Internet protocol, and Gigabit Ethernet) for
bandwidths of OC-192 ATM, POS, and 10-Gigabit Ethernet applications.
Some key POS-PHY Level 4 system features include:
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POS-PHY Level 4 operates at a wide range of frequencies.
OIF-SFI4.1
This implementation agreement is widely used in the industry for
interfacing physical layer (PHY) to the serializer-deserializer (SERDES)
devices in OC-192 and 10 Gbps multi-service systems. The POS-PHY
Level 4 interface standard defines the SFI-4 standard. POS-PHY
Level 4: SFI-4 is a standardized 16-bit
10-Gbps applications. Internet LAN and WAN architectures use
telecommunication SONET protocols for data transferring data over the
PHY layer. SFI-4 interfaces between OC-192 SERDES and SONET
framers.
Large selection of POS-PHY Level 4-based PHYs
Independent of data protocol
Wide industry support
LVDS I/O standard to improve signal integrity
Inband addressing/control
Out of band flow control
Scalable architecture
Over 622-Mbps operation
Dynamic interface timing mode
Selectable I/O Standards in Stratix & Stratix GX Devices
Stratix Device Handbook, Volume 2
622-Mbps line-side interface for
4–15
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