EP1S40B956C5 Altera, EP1S40B956C5 Datasheet - Page 594
EP1S40B956C5
Manufacturer Part Number
EP1S40B956C5
Description
IC STRATIX FPGA 40K LE 956-BGA
Manufacturer
Altera
Series
Stratix®r
Datasheet
1.EP1S10F484I6N.pdf
(864 pages)
Specifications of EP1S40B956C5
Number Of Logic Elements/cells
41250
Number Of Labs/clbs
4125
Total Ram Bits
3423744
Number Of I /o
683
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
956-BGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
Available stocks
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Part Number
Manufacturer
Quantity
Price
Part Number:
EP1S40B956C5
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
- Current page: 594 of 864
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Finite Impulse Response (FIR) Filters
Figure 7–9. TDM FIR Filter Implementation
Note to
(1)
7–16
Stratix Device Handbook, Volume 2
Clock input
(1x clock)
x(n)
x x
To increase the DSP block performance, include the pipeline and output registers. See
details.
Figure
Shift register
D
D
D
D
D
D
D
7–9:
PLL
Q
Q
Q
Q
Q
Q
Q
1x clock
2x clock
If the TDM factor is more than 2, then a multiply-accumulator needs to be
implemented. This multiply-accumulator can be implemented using the
soft logic outside the DSP block if all the multipliers of the DSP block are
needed. Alternatively, the multiply-accumulator may be implemented
inside the DSP block if all the multipliers of the DSP block are not needed.
The accumulator needs to be zeroed at the start of each new sample input.
The user also needs a way to store additional sample inputs in memory.
For example, consider a sample rate of r and TDM factor of 4. Then, the
Filter coefficients
RAM / ROM 0
RAM / ROM 2
RAM / ROM 1
Note (1)
D
D
D
D
D
D
D
D
Q
Q
Q
Q
Q
Q
Q
Q
DSP block
Figure 7–3 on page 7–8
Altera Corporation
D
Accumulator
September 2004
Q
Filter output
y(n)
for
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