EP1S40B956C5 Altera, EP1S40B956C5 Datasheet - Page 592
EP1S40B956C5
Manufacturer Part Number
EP1S40B956C5
Description
IC STRATIX FPGA 40K LE 956-BGA
Manufacturer
Altera
Series
Stratix®r
Datasheet
1.EP1S10F484I6N.pdf
(864 pages)
Specifications of EP1S40B956C5
Number Of Logic Elements/cells
41250
Number Of Labs/clbs
4125
Total Ram Bits
3423744
Number Of I /o
683
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
956-BGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
Available stocks
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Part Number
Manufacturer
Quantity
Price
Part Number:
EP1S40B956C5
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
- Current page: 592 of 864
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Finite Impulse Response (FIR) Filters
7–14
Stratix Device Handbook, Volume 2
Table 7–7. Operation of TDM Filter (Shown in
2 Clock
Cycle of
0
1
2
3
4
5
6
7
y
y
y
y
y
y
y
y
0
1
2
3
4
5
6
7
= x(n-1)h(1) + x(n-3)h(3) + x(n-5)h(5) + x(n-7)h(7)
= x(n)h(0)
= x(n)h(1)
= x(n+1)h(0) + x(n-1)h(2) + x(n-3)h(4) + x(n-5)h(6)
= x(n+1)h(1) + x(n-1)h(3) + x(n-3)h(5) + x(n-5)h(7)
= x(n+2)h(0) + x(n)h(2)
= x(n+2)h(1) + x(n)h(3) + x(n-2)h(5) + x(n-4)h(7)
= x(n+3)h(0) + x(n+1)h(2) + x(n-1)h(4) + x(n-3)h(6) Generate output
Figure 7–7. Block Diagram of 8-Tap FIR Filter with TDM Factor of n=2
TDM Filter Implementation
TDM FIR filters are implemented in Stratix and Stratix GX devices by
configuring the DSP blocks in the multiplier-adder mode.
shows the implementation of an 8-tap TDM FIR filter (n=2) with 18 bits
of data and coefficient inputs. Because the input data needs to be loaded
into the DSP block in parallel, a shift register chain is implemented using
a combination of logic cells and the altshift_taps function. This shift
register is clocked with the same data sample rate (clock 1 ). The filter
coefficients are stored in ROM and loaded into the DSP block in parallel
as well. Because the TDM factor is 2, both the ROM and DSP block are
clocked with clock 2 .
Figure 7–8
example, during cycle 0, only the flip-flops corresponding to h(1), h(3),
h(5), and h(7) are enabled. This produces the temporary output, y
is stored in a flip-flop outside the DSP block. During cycle 1, only the flip-
+ x(n-2)h(2) + x(n-4)h(4) + x(n-6)h(6)
+ x(n-2)h(3) + x(n-4)h(5) + x(n-6)h(7)
18-bit input
Cycle Output
2x clock
and
+ x(n-2)h(4) + x(n-4)h(6)
Table 7–7
Figure 7–9 on page
four multipliers
FIR filter with
show the coefficient loading schedule. For
7–16)
Store result
Generate output
Store result
Store result
Store result
Generate output
Generate output
D
Operation
Q
Altera Corporation
September 2004
N/A
y(n) = y
N/A
y(n) = y
N/A
y(n) = y
N/A
y(n) = y
Overall Output,
Figure 7–9
Output
y(n)
0
0
2
4
6
, which
+ y
+ y
+ y
+ y
1
3
5
7
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