EP1S40B956C5 Altera, EP1S40B956C5 Datasheet - Page 640

• Manufacturer Part Number: EP1S40B956C5
• Description: IC STRATIX FPGA 40K LE 956-BGA
• Manufacturer: Altera
• Series: Stratix®r

Specifications of EP1S40B956C5

• Number Of Logic Elements/cells: 41250
• Number Of Labs/clbs: 4125
• Total Ram Bits: 3423744
• Number Of I /o: 683
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 956-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -

Conclusion
Conclusion
7–62
Stratix Device Handbook, Volume 2
Arithmetic Function Implementation Results
Table 7–19
with the PIPELINE parameter set to YES.
the implementation shown in
set to NO.
Arithmetic Function Design Example
Download the Vector Magnitude Function (magnitude.zip) design
example from the Design Examples section of the Altera web site at
www.altera.com.
The DSP blocks in Stratix and Stratix GX devices are optimized to support
DSP functions requiring high data throughput, such as FIR filters, IIR
filters and the DCT. The DSP blocks are flexible and configurable in
different operation modes based on the application’s needs. The
TriMatrix memory provides the data storage capability often needed in
DSP applications.
The DSP blocks and TriMatrix memory in Stratix and Stratix GX devices
offer performance and flexibility that translates to higher performance
DSP functions.
Part
Utilization
Performance
Latency
Part
Utilization
Performance
Latency
Table 7–19. Vector Magnitude Function Implementation Results
(PIPELINE=YES)
Table 7–20. Vector Magnitude Function Implementation Results
(PIPELINE=NO)
shows the results of the implementation shown in
EP1S10F780
Lcell: 497/10570 (4%)
DSP block 9-bit elements: 2/48 (4%)
Memory bits: 0/920448 (0%)
194 MHz
15 clock cycles
EP1S10F780
Lcell: 244/10570 (2%)
DSP block 9-bit elements: 2/48 (4%)
Memory bits: 0/920448 (0%)
30 MHz
3 clock cycles
Figure 7–38
Table 7–20
with the PIPELINE parameter
shows the results of
Altera Corporation
September 2004
Figure 7–38