EP1S40B956C5 Altera, EP1S40B956C5 Datasheet - Page 681

• Manufacturer Part Number: EP1S40B956C5
• Description: IC STRATIX FPGA 40K LE 956-BGA
• Manufacturer: Altera
• Series: Stratix®r

Specifications of EP1S40B956C5

• Number Of Logic Elements/cells: 41250
• Number Of Labs/clbs: 4125
• Total Ram Bits: 3423744
• Number Of I /o: 683
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 956-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -

Figure 9–9. Framer Receiver Timing Diagram
Altera Corporation
July 2005
TX_CLK
Data invalid window before the rising edge (T
Data invalid window after the rising edge (T
TX_CLK
Framer transmitter channel-to-channel skew
RX_DATA[15..0]
Table 9–5. SFI-4 Framer Transmitter 2 (311 MHz Clock) Mode Timing Specifications
RX_CLK(P)
T cq_pre
(T
duty cycle
period
)
Parameter
T cq_post
Valid
Data
Figure 9–8
Figure 9–8. Framer Transmitter 2 (311 MHz Clock) Mode Timing Diagram
Table 9–5
Figure 9–9
T period
2 (311 MHz clock) mode
2 (311 MHz clock) mode.
T setup
TX_DATA[15..0]
lists the timing specifications for the SFI-4 framer transmitter in
TX_CLK(P)
shows the timing diagram for the SFI-4 framer transmitter in
shows the timing diagram for the SFI-4 framer receiver.
cq_post
T hold
cq_pre
T cq_pre
)
)
Transmitter Channel-to-Channel
RX_DATA[15..0]
Implementing SFI-4 in Stratix & Stratix GX Devices
Min
48
RX_CLK(P)
Skew/2
T cq_post
T period/2
Valid
Data
Value
3,215
Typ
RSKM
Stratix Device Handbook, Volume 2
Sampling Window
Tperiod
Max
200
200
200
RSKM
52
Valid
Data
Transmitter Channel-to-Channel
Skew/2
Unit
ps
ps
ps
ps
%
9–11