EP1S40B956C5 Altera, EP1S40B956C5 Datasheet - Page 676
EP1S40B956C5
Manufacturer Part Number
EP1S40B956C5
Description
IC STRATIX FPGA 40K LE 956-BGA
Manufacturer
Altera
Series
Stratix®r
Datasheet
1.EP1S10F484I6N.pdf
(864 pages)
Specifications of EP1S40B956C5
Number Of Logic Elements/cells
41250
Number Of Labs/clbs
4125
Total Ram Bits
3423744
Number Of I /o
683
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
956-BGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
EP1S40B956C5
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
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Introduction
Figure 9–4. Implementation of SFI-4 Interface Using Stratix & Stratix GX Devices
9–6
Stratix Device Handbook, Volume 2
Logic Array
Stratix GX
Stratix &
Data
Data
Clk
Clk
f
Transmitter
Receiver
Stratix Framer
128
128
For details on differential I/O buffers, SERDES, and clock dividers using
PLLs, see the High-Speed Differential I/O Interfaces in Stratix Devices
chapter in the Stratix Device Handbook or the Stratix GX Device Handbook.
Figure 9–5
framer interface implemented in Stratix and Stratix GX devices. The data
starts in the logic array and goes into the Stratix and Stratix GX SERDES
block. The transmitter SERDES of the framer converts the parallel data to
serial data for the 16 TXDATA channels (TXDATA[15..0]). A fast PLL is
used to generate TXCLK from TXCLK_SRC. The fast PLL keeps the
TXDATA and TXCLK edge-aligned. A divided down ( 8) clock generated
from TXCLK_SRC is used to convert the parallel data to serial in the
transmitter SERDES. The divided down clock also clocks some of the
logic in the logic array.
PLL2
÷8
PLL1
Transmitter
SERDES
÷8
Receiver
SERDES
Phase Shift
shows the transmitter block (from
180˚
×1
RXDATA[15..0]
TXDATA[15..0]
TXCLK_SRC
TXCLK
RXCLK
REFCLK
Figure
SERDES
9–4) of the SFI-4
OC-192
Altera Corporation
Transmitter
Receiver
July 2005
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