EP1S40B956C5 Altera, EP1S40B956C5 Datasheet - Page 623
![IC STRATIX FPGA 40K LE 956-BGA](/photos/6/73/67334/544-stratix_956-bga_sml.jpg)
EP1S40B956C5
Manufacturer Part Number
EP1S40B956C5
Description
IC STRATIX FPGA 40K LE 956-BGA
Manufacturer
Altera
Series
Stratix®r
Datasheet
1.EP1S10F484I6N.pdf
(864 pages)
Specifications of EP1S40B956C5
Number Of Logic Elements/cells
41250
Number Of Labs/clbs
4125
Total Ram Bits
3423744
Number Of I /o
683
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
956-BGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
EP1S40B956C5
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
- Current page: 623 of 864
- Download datasheet (11Mb)
Matrix
Manipulation
Altera Corporation
September 2004
Implementing High Performance DSP Functions in Stratix & Stratix GX Devices
Butterworth Filter Implementation Results
Table 7–16
filter as shown in
Butterworth Filter Design Example
Download the 4
example from the Design Examples section of the Altera web site at
www.altera.com.
DSP relies heavily on matrix manipulation. The key idea is to transform
the digital signals into a format that can then be manipulated
mathematically.
This section describes an example of matrix manipulation used in 2-D
convolution filter, and its implementation in a Stratix device.
Background on Matrix Manipulation
A matrix can represent all digital signals. Apart from the convenience of
compact notation, matrix representation also exploits the benefits of
linear algebra. As with one-dimensional, discrete sequences, this
advantage becomes more apparent when processing multi-dimensional
signals.
In image processing, matrix manipulation is important because it
requires analysis in the spatial domain. Smoothing, trend reduction, and
sharpening are examples of common image processing operations, which
are performed by convolution. This can also be viewed as a digital filter
operation with the matrix of filter coefficients forming a convolutional
kernel, or mask.
Part
Utilization
Performance
Latency
Table 7–16. 4
shows the results of implementing a 4
th
Order Butterworth Filter Implementation Results
th
Figure
Order Butterworth Filter (butterworth.zip) design
EP1S10F780C6
Lcell: 251/10570(2%)
DSP Block 9-bit elements: 16/48 (33%)
Memory bits: 0/920448 (0%)
80 MHz
4 clock cycles
7–25.
Stratix Device Handbook, Volume 2
th
order Butterworth
7–45
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