EP1S40B956C5 Altera, EP1S40B956C5 Datasheet - Page 480
EP1S40B956C5
Manufacturer Part Number
EP1S40B956C5
Description
IC STRATIX FPGA 40K LE 956-BGA
Manufacturer
Altera
Series
Stratix®r
Datasheet
1.EP1S10F484I6N.pdf
(864 pages)
Specifications of EP1S40B956C5
Number Of Logic Elements/cells
41250
Number Of Labs/clbs
4125
Total Ram Bits
3423744
Number Of I /o
683
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
956-BGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
EP1S40B956C5
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
- Current page: 480 of 864
- Download datasheet (11Mb)
Principles of SERDES Operation
Figure 5–3. Stratix High-Speed Interface Deserialized in
Notes to
(1)
(2)
Figure 5–4. Receiver Timing Diagram
5–8
Stratix Device Handbook, Volume 2
RXCLKIN+
RXCLKIN−
W = 1, 2, 4, 7, 8, or 10.
J = 4, 7, 8, or 10.
W does not have to equal J. When J = 1 or 2, the deserializer is bypassed. When J = 2, the device uses DDRIO registers.
This figure does not show additional circuitry for clock or data manipulation.
Internal ×10 clock
Internal ×10 clock
Internal ×1 clock
Internal ×1 clock
RXIN+
RXIN−
Figure
RXLOADEN
RXLOADEN
data input
data input
Receiver
Receiver
5–3:
Receiver Circuit
n – 1
n – 1
PLL (2)
Fast
Serial Shift
Registers
n – 0
n – 0
RXLOADEN
TXLOADEN
× W
9
9
PD0
PD1
PD2
PD3
PD4
PD5
PD6
PD7
PD9
PD8
8
8
Registers
Parallel
7
7
×
10 Mode
6
6
PD0
PD1
PD2
PD3
PD4
PD5
PD6
PD7
PD9
PD8
× W / J (1)
5
5
Registers
Parallel
4
4
3
3
PD0
PD1
PD2
PD3
PD4
PD5
PD6
PD7
PD9
PD8
2
2
Altera Corporation
1
1
Logic Array
Stratix
0
0
July 2005
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