EP1S40B956C5 Altera, EP1S40B956C5 Datasheet - Page 346

• Manufacturer Part Number: EP1S40B956C5
• Description: IC STRATIX FPGA 40K LE 956-BGA
• Manufacturer: Altera
• Series: Stratix®r

Specifications of EP1S40B956C5

• Number Of Logic Elements/cells: 41250
• Number Of Labs/clbs: 4125
• Total Ram Bits: 3423744
• Number Of I /o: 683
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 956-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -

Fast PLLs
1–36
Stratix Device Handbook, Volume 2
The equation to determine the precision of phase in degrees is: 45
scale counter value. Therefore, the maximum step size is 45 , and smaller
steps are possible depending on the multiplication and division ratio
necessary on the output counter port.
This type of phase shift provides the highest precision since it is the least
sensitive to process, supply, and temperature variation.
Programmable Duty Cycle
The programmable duty cycle allows the fast PLL to generate clock
outputs with a variable duty cycle. This feature is supported on each fast
PLL post-scale counter. g0, l0, and l1 all support programmable duty. You
use a low- and high-time count setting for the post-scale counters to set
the duty cycle.
The Quartus II software uses the frequency input and multiply/divide
rate desired to select the post-scale counter, which determines the
possible choices for each duty cycle. The precision of the duty cycle is
determined by the post-scale counter value chosen on an output. The
precision is defined by 50% divided by the post-scale counter value. The
closest value to 100% is not achievable for a given counter value. For
example, if the g0 counter is 10, then steps of 5% are possible for duty
cycle choices between 5 to 90%.
If the device uses external feedback, you must set the duty cycle for the
counter driving off the device to 50%.
Control Signals
The lock output indicates a stable clock output signal in phase with the
reference clock. Unlike enhanced PLLs, fast PLLs do not have a lock filter
counter.
The pllenable pin is a dedicated pin that enables/disables both PLLs.
When the pllenable pin is low, the clock output ports are driven by
GND and all the PLLs go out of lock. When the pllenable pin goes high
again, the PLLs relock and resynchronize to the input clocks. You can
choose which PLLs are controlled by the pllenable by connecting the
pllenable input port of the altpll megafunction to the common
pllenable input pin.
The areset signals are reset/resynchronization inputs for each fast PLL.
The Stratix and Stratix GX devices can drive these input signals from an
input pin or from LEs. When driven high, the PLL counters reset, clearing
the PLL output and placing the PLL out of lock. The VCO sets back to its
nominal setting (~700 MHz). When driven low again, the PLL
Altera Corporation
July 2005
post-