EP1S40B956C5 Altera, EP1S40B956C5 Datasheet - Page 733
![IC STRATIX FPGA 40K LE 956-BGA](/photos/6/73/67334/544-stratix_956-bga_sml.jpg)
EP1S40B956C5
Manufacturer Part Number
EP1S40B956C5
Description
IC STRATIX FPGA 40K LE 956-BGA
Manufacturer
Altera
Series
Stratix®r
Datasheet
1.EP1S10F484I6N.pdf
(864 pages)
Specifications of EP1S40B956C5
Number Of Logic Elements/cells
41250
Number Of Labs/clbs
4125
Total Ram Bits
3423744
Number Of I /o
683
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
956-BGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
EP1S40B956C5
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
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Figure 11–5. PS Configuration Circuit with a Download Cable
Notes to
(1)
(2)
(3)
Altera Corporation
July 2005
You should connect the pull-up resistor to the same supply voltage as the MasterBlaster (VIO pin) or ByteBlasterMV
cable.
The pull-up resistors on the DATA0 and DCLK pins are only needed if the download cable is the only configuration
scheme used on the board. This is to ensure that the DATA0 and DCLK pins are not left floating after configuration.
For example, if the design also uses a configuration device, the pull-up resistors on the DATA0 and DCLK pins are
not necessary.
Pin 6 of the header is a V
V
CCIO
Figure
. This pin is a no-connect pin for the ByteBlasterMV header.
(2)
V CC (1)
10 kΩ
11–5:
10 kΩ
V CC (1)
(2)
(2)
V CC (1)
IO
10 kΩ
reference voltage for the MasterBlaster output driver. V
You can use programming hardware to configure multiple Stratix and
Stratix GX devices by connecting each device’s nCEO pin to the
subsequent device’s nCE pin. All other configuration pins are connected
to each device in the chain.
Because all CONF_DONE pins are tied together, all devices in the chain
initialize and enter user mode at the same time. In addition, because the
nSTATUS pins are tied together, the entire chain halts configuration if any
device detects an error. In this situation, the Quartus II software must
restart configuration; the Auto-Restart Configuration on Frame Error
option does not affect the configuration cycle.
Figure 11–6
devices with a MasterBlaster or ByteBlasterMV cable.
GND
V CC
MSEL2
MSEL1
MSEL0
nCE
DCLK
DATA0
nCONFIG
Stratix GX Device
Stratix or
shows how to configure multiple Stratix and Stratix GX
CONF_DONE
nSTATUS
nCEO
N.C.
V CC (1)
10 kΩ
Configuring Stratix & Stratix GX Devices
V CC (1)
Stratix Device Handbook, Volume 2
10 kΩ
Pin 1
IO
10-Pin Male Header
should match the device’s
Download Cable
Shield
GND
(PS Mode)
V CC
VIO (3)
GND
11–15
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