EP1S40B956C5 Altera, EP1S40B956C5 Datasheet - Page 610

IC STRATIX FPGA 40K LE 956-BGA

EP1S40B956C5

Manufacturer Part Number
EP1S40B956C5
Description
IC STRATIX FPGA 40K LE 956-BGA
Manufacturer
Altera
Series
Stratix®r
Datasheet

Specifications of EP1S40B956C5

Number Of Logic Elements/cells
41250
Number Of Labs/clbs
4125
Total Ram Bits
3423744
Number Of I /o
683
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
956-BGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-

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Finite Impulse Response (FIR) Filters
7–32
Stratix Device Handbook, Volume 2
where:
In complex representation, this equals:
The overall real channel output is obtained by adding the real channel
outputs of all the multipliers. Similarly, the overall imaginary channel
output is obtained by adding the imaginary channel outputs of all the
multipliers.
Figure 7–18. Complex FIR Filter Block Diagram
Complex FIR Filter Implementation
Complex filters can be easily implemented in Stratix devices with the DSP
blocks configured in the two-multipliers adder mode. One DSP block can
implement a 2-tap complex FIR filter with 9-bit inputs, or a single tap
complex FIR filter with 18-bit inputs. DSP blocks can be cascaded to
implement complex filters with more taps.
1
x
x
h
h
y
y
y
y
y
real
imag
real
imag
real
imag
real
imag
real
is the real input signal
is the real filter coefficients
is the real output signal
The two-multipliers adder mode has two adders, each adding
the outputs of two multipliers. One of the adders is configured
as a subtractor.
is the imaginary input signal
is the imaginary filter coefficients
is the imaginary output signal
+
=
=
jy
x
imag
x
real
real
x imag
x real
=
h
h
real
x
imag
real
+
+
x
imag
h
jx
real
imag
h real
Complex
FIR filter
h
x
imag
imag
h imag
h
real
+
jh
imag
y real
y imag
Altera Corporation
September 2004

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