IPR-PCIE/8 Altera, IPR-PCIE/8 Datasheet - Page 96

• Manufacturer Part Number: IPR-PCIE/8
• Description: IP CORE Renewal Of IP-PCIE/8
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCIE/8

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Express Compiler, x8 Link Width
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Signals
Figure 3–20. 64-Bit Memory Write Request Waveform
3–58
PCI Express Compiler User Guide
Descriptor
Signals
Signals
Data
tx_desc[127:0]
tx_data[63:32]
tx_data[31:0]
tx_ack
tx_req
tx_ws
tx_err
tx_dfr
tx_dv
Priority Given Elsewhere
In this example, the application transmits a 64-bit memory write
transaction of 8 DWORDS. Address bit 2 is set to 0. The transmit path has
a 3-deep 64-bit buffer to handle back-to-back transaction layer packets as
fast as possible, and it accepts the tx_desc and first tx_data without
delay. See
In clock cycle 5, the MegaCore function asserts
throttle the flow of data because priority was not given immediately to
this virtual channel. Priority was given to either a pending data link layer
packet, a configuration completion, or another virtual channel. The
tx_err is not available in the x8 MegaCore function.
1
X
X
PCI Express Compiler Version 6.1
2
MEMWR64
Figure
3
DW1
DW0
4
3–20.
5
6
Clock Cycles
7
DW3
DW2
8
9
10
DW5
DW4
11
DW7
DW6
tx_ws
12
13
a second time to
Altera Corporation
14
December 2006
X
X
15