IPR-PCIE/8 Altera, IPR-PCIE/8 Datasheet - Page 108

• Manufacturer Part Number: IPR-PCIE/8
• Description: IP CORE Renewal Of IP-PCIE/8
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCIE/8

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Express Compiler, x8 Link Width
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Signals
Figure 3–27. Transaction with a Data Payload Waveform
3–70
PCI Express Compiler User Guide
Descriptor
Signals
Signals
Data
rx_desc[135:128]
rx_desc[127:64]
rx_data[63:32]
rx_desc[63:0]
rx_data[31:0]
rx_be[7:0]
rx_mask
rx_abort
rx_retry
rx_ack
rx_req
rx_ws
Transaction with Data Payload
In
of 8 DWORDS and a second memory write request of 3 DWORDS. Bit 2
of rx_data[63:0] is set to 0 for the completion transaction and to 1 for
the memory write request transaction.
Normally, rx_dfr is asserted on the same or following clock cycle as
rx_req; however, in this case the signal is already asserted until clock
cycle 7 to signal the end of transmission of the first transaction. It is
immediately reasserted on clock cycle 8 to request a data phase for the
second transaction.
rx_dfr
rx_dv
Figure
X
X
X
1
PCI Express Compiler Version 6.1
3–27, the MegaCore function receives a completion transaction
X
X
X
2
CPLD 8DW
3
Valid
Valid
4
DW 1
DW 0
X
X
X
5
DW 3
DW 2
6
DW 5
DW 4
Clock Cycles
FFh
MEMWR AD1 3DW
7
DW 6
DW 7
8
Valid
Valid
X
9
X
10
DW 0
F0h
11
DW 2
FFh
DW 1
12
X
X
X
Altera Corporation
13
X
X
X
December 2006
14