IPR-PCIE/8 Altera, IPR-PCIE/8 Datasheet - Page 35

• Manufacturer Part Number: IPR-PCIE/8
• Description: IP CORE Renewal Of IP-PCIE/8
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCIE/8

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Express Compiler, x8 Link Width
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Getting Started
Altera Corporation
December 2006
Notes to
(1)
(2)
<
<
<
<
<variation name>_core.vho or
or <variation name>_core.vo
Table 2–2. Generated Files
variation name
variation name
variation name
variation name
These files are variation dependent, some may be absent or their names may change.
<variation name> is a prefix variation name supplied automatically by the MegaWizard Plug-In Manager.
Table
2–1:
>
>
>
>
.vhd or
.v
_core.vhd or
_core.v
Filename
Notes (1)& (2)
You can now integrate your custom MegaCore function variation into
your design, simulate, and compile.
Quartus II software also creates a three-level subdirectory in your project
directory named <variation name>_examples.
directory structure. This subdirectory contains a PCI Express BFM and
testbench for testing both the Simple DMA example design and the
chaining DMA example design. The directory also includes scripts for
running the testbench in the ModelSim simulator. See
Testbench & Example Designs
created for the testbench.
PCI Express Compiler Version 6.1
(Part 2 of 2)
This file instantiates the <variation name>_core
module (or entity) that is described elsewhere in this
table and includes additional logic required to support
the specific external or internal PHY you have chosen
for your variation. You must instantiate this file inside of
your design. You should include this file when you
compile your design in the Quartus II software and in
your simulation project.
This file instantiates the PCI Express Transaction, Data
Link, and Physical layers. It is instantiated inside the
<variation name> module (or entity). Include this file
when you compile your design in the Quartus II
software.
This file includes the VHDL or Verilog HDL IP functional
simulation model of the <variation name>_core entity
(or module). Include this file when simulating your
design.
for a list and brief description of the files
PCI Express Compiler User Guide
Description
Figure 2–11
Chapter 5,
illustrates this
2–13