IPR-PCIE/8 Altera, IPR-PCIE/8 Datasheet - Page 178

• Manufacturer Part Number: IPR-PCIE/8
• Description: IP CORE Renewal Of IP-PCIE/8
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCIE/8

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Express Compiler, x8 Link Width
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Root Port BFM
5–28
PCI Express Compiler User Guide
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A set of procedures is provided to read, write, fill, and check the
shared memory from the BFM driver. For details on these
procedures, see
page
BFM Read/Write Request Procedures/Functions
(altpcietb_bfm_rdwr VHDL package or Verilog HDL include file) —
This package provides the basic BFM procedure calls to request PCI
Express read and write requests. For details on these procedures, see
“BFM Read/Write Request Procedures” on page
BFM Configuration Procedures/Functions
(altpcietb_bfm_configure VHDL package or Verilog HDL include
file) — These procedures and functions provide the BFM calls to
request configuration of the PCI Express link and the endpoint
configuration space registers. For details on these procedures and
functions, see
BFM Log Interface (altpcietb_bfm_log VHDL package or Verilog
HDL include file) — The BFM log interface provides routines for
writing commonly formatted messages to the simulator standard
output and optionally to a log file. It also provides controls that stop
simulation on errors. For details on these procedures, see
& Message Procedures” on page
BFM Request Interface (altpcietb_bfm_req_intf VHDL package or
Verilog HDL include file) — This interface provides the low level
interface between the altpcietb_bfm_rdwr and
altpcietb_bfm_configure procedures or functions and the root
port RTL Model. This interface stores a write-protected data
structure containing the sizes and the values programmed in the
BAR registers of the endpoint, as well as, other critical data used for
internal BFM management. You do not need to access these files
directly to adapt the testbench to test your endpoint application.
Root Port RTL Model (altpcietb_bfm_rp_top_x8_pipen1b VHDL
entity or Verilog HDL Module) — This is the Register Transfer Level
(RTL) portion of the model. This takes the requests from the above
PCI Express Compiler Version 6.1
Sourcing data for most write transactions issued to the PCI
Express link. The only exception is certain BFM write
procedures that have a four-byte field of write data passed in the
call.
Storing a data structure that contains the sizes of and the values
programmed in the BARs of the endpoint
5–46.
“BFM Configuration Procedures” on page
“BFM Shared Memory Access Procedures” on
5–50.
5–42.
Altera Corporation
December 2006
5–44.
“BFM Log