IPR-PCIE/8 Altera, IPR-PCIE/8 Datasheet - Page 141

• Manufacturer Part Number: IPR-PCIE/8
• Description: IP CORE Renewal Of IP-PCIE/8
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCIE/8

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Express Compiler, x8 Link Width
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

External PHYs
Figure 4–5. 8-bit SDR Mode
Altera Corporation
December 2006
clk125_in
clk125_out
refclk (250 Mhz)
rxdata
txdata
External connection in user logic
Mode 4
PLL
8-bit SDR with a Source Synchronous TxClk
The implementation of the 16-bit SDR mode with a source synchronous
TxClk is shown in
<variation name>.v or <variation name>.vhd and includes a PLL. The PLL
inclock is driven by refclk (pclk from the external PHY) and has the
following 3 outputs:
■
■
Q 1
Q 4
Edge Detect and Sync
250Mhz SDR Mode
A
D
0
0
ENB
A 125 MHz output derived from the 250 MHz refclk. This 125
MHz PLL output is used as the clk125_in for the MegaCore
function.
A 250 MHz "early" output that is skewed early in relation to the
refclk the 250 MHz early clock PLL output is used to clock an 8-bit
SDR transmit data output register.
PCI Express Compiler Version 6.1
ENB
0
0
0
A
D
Q 1
Q 4
Q 1
Q 4
Figure 4–6
A
D
A
D
ENB
clk250_early
ENB
ENB
A
D
Q 1
Q 4
Q 1
Q 4
tlp_clk
and is included in the file
A
D
A
D
ENB
ENB
txdata_h
txdata_l
PCI Express Compiler User Guide
Q 1
Q 4
Q 1
Q 4
PCIe IP MegaCore
rxdata_l
clk125_in
tlp_clk
refclk
rxdata_h
4–9