IPR-PCIE/8 Altera, IPR-PCIE/8 Datasheet - Page 224

• Manufacturer Part Number: IPR-PCIE/8
• Description: IP CORE Renewal Of IP-PCIE/8
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCIE/8

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Express Compiler, x8 Link Width
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Configuration Signals for x8 MegaCore Functions
A–8
PCI Express Compiler User Guide
k_conf[115:113]
k_conf[119:116]
k_conf[127:120]
k_conf[130:128]
k_conf[132:131]
k_conf[133]
k_conf[136:134]
k_conf[139:137]
k_conf[143:140]
k_conf[145:144]
k_conf[151:146]
k_conf[153:152]
k_conf[156:154]
k_conf[159:157]
k_conf[166:160]
k_conf[169:167]
k_conf[191:170]
Table A–2. Configuration Signals for x8 MegaCore Functions
Signal
Buffer Setup:
Low Priority
Virtual Channels
Fixed to 0b0001 Port VC capability register 2 VC arbitration capability field.
Fixed to 0
Fixed to 0
Fixed to 0
Fixed to 0
Power
Management:
Endpoint L0s
Acceptable
Latency
Power
Management:
Endpoint L1
Acceptable
Latency
Fixed to 0
Fixed to 0
Calculated from
the number of
lanes
Power
Management:
Enable L1
ASPM
Power
Management:
L1 Exit Latency
Common Clock
Power
Management:
L1 Exit Latency
Separate Clock
Fixed to 0
Capabilities:
Tags Supported
Fixed to 0
Value or Wizard
Page/Label
PCI Express Compiler Version 6.1
Port VC capability register 1 low priority VC field.
Reserved.
Reserved.
Reserved.
Reserved.
Device capabilities register: endpoint L0s acceptable latency. 0 =
< 64 ns, 1 = 64 - 128 ns, 2 = 128 - 256 ns, 3 = 256 - 512 ns, 4 =
512 ns - 1 μs, 5 = 1 - 2 μs, 6 = 2 - 4 μs, 7 => 4 μs.
Device capabilities register: endpoint L1 acceptable latency. 0 =<
1 μs, 1 = 1 - 2 μs, 2 = 2 - 4 μs, 3 = 4 - 8 μs, 4 = 8 - 16 μs, 5 = 16
- 32 μs, 6 = 32 - 64 μs, 7 => 64 μs.
Reserved.
Reserved.
Link capabilities register: maximum link width. 1 = x1, 4 = x4,
others = reserved.
Link capabilities register: active state power management
support. 01 = L0s, 11 = L1 and L0s.
Link capabilities register: L1 exit latency - separate clock. 0 =< 1
μs, 1 = 1 - 2 μs, 2 = 2 - 4 μs, 3 = 4 - 8 μs, 4 = 8 - 16 μs, 5 = 16 -
32 μs, 6 = 32 - 64 μs, 7 =>64 μs.
Link capabilities register: L1 exit latency - common clock. 0 =< 1
μs, 1 = 1 - 2 μs, 2 = 2 - 4 μs, 3 = 4 - 8 μs, 4 = 8 - 16 μs, 5 = 16 -
32 μs, 6 = 32 - 64 μs, 7 => 64 μs.
Reserved.
Number of tags supported for non-posted requests transmitted.
Reserved.
Description
Altera Corporation
December 2006