IPR-PCIE/8 Altera, IPR-PCIE/8 Datasheet - Page 161

• Manufacturer Part Number: IPR-PCIE/8
• Description: IP CORE Renewal Of IP-PCIE/8
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCIE/8

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Express Compiler, x8 Link Width
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Testbench & Example Designs
Chaining DMA
Example Design
Altera Corporation
December 2006
This example design shows how to create a chaining DMA endpoint in
which two DMA modules support simultaneous DMA read and write
transactions. One DMA module implements write operations on the
upstream flow from Endpoint (EP) memory to Root Complex (RC)
memory, and the other DMA implements read operations on the
downstream flow from RC memory to EP memory.
The chaining DMA example design endpoint design is completely
contained within a supported Altera device and relies on no other
hardware interface than the PCI Express link. This allows you to use the
example design for the initial hardware validation of your system.
The MegaWizard interface generates the example design in the same
language that you used for the variation (generated by the variation name
file); the example design is either Verilog HDL or VHDL. The chaining
DMA design example requires that BAR 2 or BAR 3 is set to a minimum
of 256 bytes.
During the generate step, the example endpoint design is created with the
MegaCore function variation. The example design includes two main
components:
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In the simple DMA example design, the software application (on the root
port side) needs to program the end point DMA registers for every
transfer of a given block of memories. This can introduce a performance
limitation when transferring a large amount of noncontiguous memory
between the BFM shared memory and the Endpoint buffer memory. The
chaining DMA example design shows an architecture which is capable of
transferring a large amount of fragmented memory without
reprogramming the DMA registers for every memory block.
The chaining DMA example design uses descriptor tables for each block
of memory to be transferred. Each descriptor table contains the following
information
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The MegaCore function variation
An application layer example design
Length of the transfer
Address of the source
Address of the destination
Control bits to set the handshaking behavior between the software
application and the chaining DMA module.
PCI Express Compiler Version 6.1
PCI Express Compiler User Guide
5–11