IPR-PCIE/8 Altera, IPR-PCIE/8 Datasheet - Page 167

• Manufacturer Part Number: IPR-PCIE/8
• Description: IP CORE Renewal Of IP-PCIE/8
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCIE/8

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Express Compiler, x8 Link Width
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Testbench & Example Designs
Table 5–5. Chaining DMA Descriptor Header Format Address Map
Table 5–6. Chaining DMA Descriptor Header Format (Control Fields)
Altera Corporation
December 2006
31
Reserved
Size
Direction
Message
Signaled
Interrupt
(MSI)
Table 5–7. Chaining DMA Descriptor Header Fields (Part 1 of 2)
Header Field
Descriptor
31
30
MSI Traffic
Class
Control Fields (see
R
R
R
Access
EP
Reserved
28 27
R/W
R/W
R/W
Access
Reserved
Chaining DMA Descriptor Tables
Each descriptor table consists of a descriptor header at a base address,
followed by a contiguous list of descriptors. Each subsequent descriptor
consists of a minimum of four DWORDs (PCI-Express 32 bit double
word) of data, and corresponds to one DMA transfer. The software
application writes the descriptor header in the EP point Header
Descriptor register.
heade
RC
Table
r.
0x00 (DMA write)
0x10 (DMA read)
0x00 (DMA write)
0x10 (DMA read)
0x00 (DMA write)
0x10 (DMA read)
PCI Express Compiler Version 6.1
5–6)
EP Address
25 24
BDT Upper DWORD
BDT Lower DWORD
MSI Number
Tables
16 15
Specifies the number n of the descriptor in the
descriptor table.
Specifies the DMA module to the descriptor table
mapping rules. When this bit is set the descriptor
table refers to the DMA write logic. When this bit is
cleared the descriptor table refers to the DMA read
logic.
Enables interrupts across all descriptors. When this
bit is set the EP DMA module issues an interrupt
using MSI to the RC. Your software application can
use this interrupt to monitor the DMA transfer status.
5–5, 5–6, and , describe each of the fields of this
20
Reserved EPLAST_ENA MSI
19
PCI Express Compiler User Guide
Description
RCLAST
Size
18
17
Direction
16
0
5–17