IPR-PCIE/8 Altera, IPR-PCIE/8 Datasheet - Page 13

• Manufacturer Part Number: IPR-PCIE/8
• Description: IP CORE Renewal Of IP-PCIE/8
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCIE/8

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Express Compiler, x8 Link Width
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

About This Compiler
General
Description
Altera Corporation
December 2006
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The PCI Express Compiler generates customized PCI Express MegaCore
functions you use to design PCI Express endpoints, including non-
transparent bridges, or truly unique designs combining multiple PCI
Express components in a single Altera device. The PCI Express MegaCore
functions are PCI Express Base Specification Revision 1.1 or PCI Express™
Base Specification Revision 1.0a compliant, and implement all required and
most optional features of the specification for the transaction, data link,
and physical layers.
The PCI Express Compiler allows you to select from 3 MegaCore
functions that support x1, x4, or x8 operation and that are suitable for
endpoint applications.
functions can be used in an example system. If you target the MegaCore
function for Stratix GX or Stratix II GX devices, the MegaCore function
includes a complete PHY layer, including the MAC, PCS, and PMA
layers. If you target other device architectures, the PCI Express Compiler
generates the MegaCore function with the Intel-designed PIPE interface,
making the MegaCore function usable with other PIPE-compliant
external PHY devices.
When selecting your external PHY, the PCI Express MegaCore functions
support a wide range of PHYs including the TI XIO1100 PHY in 8-bit
DDR mode or 16-bit SDR mode; Philips PX1011A for 8-bit SDR mode, a
serial PHY for Stratix II GX and Stratix GX devices, and a range of custom
PHYs using 8-bit/16-bit SDR with or without source synchronous
transmit cock modes and 8-bit DDR with or without source synchronous
transmit clock modes.
Access to high reliability features
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Free evaluation using OpenCore Plus
PCI Express Compiler Version 6.1
Optional end-to-end cyclic redundancy code (ECRC)/advanced
error reporting (AER) support for x1, x4, and x8 lanes
Figure 1–1
shows how the PCI Express MegaCore
PCI Express Compiler User Guide
1–3