IPR-PCIE/8 Altera, IPR-PCIE/8 Datasheet - Page 104

• Manufacturer Part Number: IPR-PCIE/8
• Description: IP CORE Renewal Of IP-PCIE/8
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCIE/8

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Express Compiler, x8 Link Width
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Signals
Figure 3–24. Three Transactions without Data Payloads Waveform
3–66
PCI Express Compiler User Guide
Descriptor
Signals
Signals
Data
rx_desc[135:128]
rx_desc[127:64]
rx_data[63:32]
rx_desc[63:0]
rx_data[31:0]
rx_be[7:0]
rx_mask
rx_abort
rx_retry
rx_ack
rx_req
rx_ws
Transaction without Data Payload
In
transactions, none of which have data payloads:
■
■
■
In clock cycles 4, 7, and 12, the MegaCore function updates flow control
credits after each transaction layer packet has either been acknowledged
or aborted. When necessary, the MegaCore function generates flow
control DLLPs to advertise flow control credit levels.
In clock cycle 8, the I/O read request initiated at clock cycle 8 is not
acknowledged until clock cycle 11 with assertion of rx_ack. The
relatively late acknowledgment could be due to possible congestion.
rx_dfr
rx_dv
Figure
Memory read request (64-bit addressing mode)
Memory read request (32-bit addressing mode)
I/O read request
1
PCI Express Compiler Version 6.1
X
X
X
3–24, the MegaCore function receives three consecutive
2
MEMRD64
3
Valid
Valid
4
X
X
X
5
MEMRD32
6
Valid
Valid
Clock Cycles
7
X
X
X
X
X
X
8
9
Valid
I/O RD
Valid
10
11
12
Altera Corporation
13
X
X
X
December 2006
14