IPR-PCIE/8 Altera, IPR-PCIE/8 Datasheet - Page 121

• Manufacturer Part Number: IPR-PCIE/8
• Description: IP CORE Renewal Of IP-PCIE/8
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCIE/8

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Express Compiler, x8 Link Width
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Specifications
Altera Corporation
December 2006
app_msi_req
app_msi_ack
app_msi_tc[2:0]
app_msi_num[4:0]
cfg_msicsr[15:0]
Table 3–33. Interrupt Signals (Part 1 of 2)
Signal
I
O
I
I
O
I/O
Table 3–33
Application MSI request. This signal is used by the application to request an MSI.
Application MSI acknowledge. This signal is sent by the MegaCore function to
acknowledge the application’s request for an MSI.
Application MSI traffic class. This signal indicates the traffic class used to send
the MSI (unlike INTx interrupts, any traffic class can be used to send MSIs).
Application MSI offset number. This signal is used by the application to indicate
the offset between the base message data and the MSI to send.
Configuration MSI control status register. This bus provides MSI software control.
●
●
●
●
●
●
cfg_msicsr[15:9]
cfg_msicsr[8]
1: function supports MSI per vector masking
0: function does not support MSI per vector masking
cfg_msicsr[7]
1: function capable of sending a 64-bit message address
0: function not capable of sending a 64-bit message address
cfg_msicsr[6:4]
permitted values for MSI signals. For example, if “100” is written to this field
16 MSI signals are allocated.
000: 1 MSI allocated
001: 2 MSI allocated
010: 4 MSI allocated
011: 8 MSI allocated
100: 16 MSI allocated
101: 32 MSI allocated
110: Reserved
111: Reserved
cfg_msicsr[3:1]
software to determine the number of requested MSI messages.
000: 1 MSI requested
001: 2 MSI requested
010: 4 MSI requested
011: 8 MSI requested
100: 16 MSI requested
101: 32 MSI requested
110: Reserved
111: Reserved
cfg_msicsr[0]
use MSI.
PCI Express Compiler Version 6.1
describes MegaCore function’s interrupt signals.
: Per vector masking capable
: 64-bit address capable
: MSI enable: If set to 0, this component is not permitted to
: Multiple message enable: This field indicates
: Multiple message capable: This field is read by system
: Reserved.
Description
PCI Express Compiler User Guide
3–83