IPR-PCIE/8 Altera, IPR-PCIE/8 Datasheet - Page 72

• Manufacturer Part Number: IPR-PCIE/8
• Description: IP CORE Renewal Of IP-PCIE/8
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCIE/8

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Express Compiler, x8 Link Width
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Parameter Settings
3–34
PCI Express Compiler User Guide
Configure Transceiver Block for Stratix II GX PHY
When you use the Stratix II GX PHY, you can configure the transceiver
block by modifying the settings in the dialog box available from
Configure transceiver block on the System Settings page.
Figure 3–8. Configure Transceiver Dialog
Enable fast recovery mode When enabled this option adds additional logic to
Enable rate match fifo
Table 3–18. Configure Transceiver Block Parameters
PCI Express Compiler Version 6.1
Parameter
allow a faster exit from the Rx ASPM L0s state.
When disabled exit from Rx ASPM L0s will typically
require link recovery to be invoked.
When enabled this option enables the Rate
Matching FIFO to allow different clocks with PPM
differences at each end of the PCI Express link.
When disabled the rate match FIFO is bypassed,
allowing for lower latency, but it is required that the
ports at both ends of the PCI Express link use the
same clock source. There can be no PPM
difference between the clocks at each end.
Description
Altera Corporation
December 2006