IPR-PCIE/8 Altera, IPR-PCIE/8 Datasheet - Page 44

• Manufacturer Part Number: IPR-PCIE/8
• Description: IP CORE Renewal Of IP-PCIE/8
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCIE/8

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Express Compiler, x8 Link Width
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Functional Description
3–6
PCI Express Compiler User Guide
Transaction Layer Routing Rules
Transactions follow these routing rules.
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Receive Buffer Bypass Mode
If the receive buffer is empty and the rx_descriptor register of a given
virtual channel does not contain valid data, the MegaCore function
bypasses the receive buffer, which decreases latency.
In reality, the receive buffer is not truly bypassed, because the descriptor
is written simultaneously to the receive buffer and the rx_descriptor
register. However, barring the need to resend the transaction layer packet,
the data in the receive buffer is never accessed.
In the receive direction (i.e., from the PCI Express link), memory and
I/O requests that match to the defined BARs route to the receive
interface. The application layer logic processes the requests and
generates the read completions, if needed.
Received type 0 configuration requests route to the internal
configuration space and the MegaCore function generates and
transmits the completion.
The MegaCore function internally handles supported received
message transactions (power management and slot power limit).
The transaction layer treats all other received transactions (including
memory or I/O requests that do not match a defined BAR) as
unsupported requests. The transaction layer sets the appropriate
error bits and transmits a completion, if needed. These unsupported
requests are not made visible to the application layer, the header and
data is dropped.
The transaction layer sends all memory and I/O requests, as well as
completions generated by the application layer and passed to the
transmit interface, to the PCI Express link.
The MegaCore function can generate and transmit power
management, interrupt, and error signaling messages automatically
under the control of dedicated signals. Additionally, the MegaCore
function can generate MSI requests under the control of the
dedicated signals.
PCI Express Compiler Version 6.1
Altera Corporation
December 2006