IPR-PCIE/8 Altera, IPR-PCIE/8 Datasheet - Page 156

• Manufacturer Part Number: IPR-PCIE/8
• Description: IP CORE Renewal Of IP-PCIE/8
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCIE/8

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Express Compiler, x8 Link Width
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Simple DMA Example Design
Figure 5–2. Top-Level Simple DMA Example Design for Simulation
5–6
PCI Express Compiler User Guide
Simple DMA Example Application Layer (altpcierd_example_app)
Simple DMA Example Design Simulation Top Level (< variation name >_example_pipenb)
Includes DMA, Memory
Includes Memory &
(altpcierd_master)
& Data Generator
Control Registers
(altpcierd_slave)
Master Module
Slave Module
altpcierd_example_app.v or altpcierd_example_app.vhd
altpcierd_master.v or altpcierd_master.vhd
altpcierd_slave.v or altpcierd_slave.vhd
<variation name>_example_pipen1b.v or
<variation name>_example_pipen1b. vhd
<variation name>_example_top.v or <variation name>_example_top.vhd
This file is created in the project directory of the generated the MegaCore
function. See
Figure 5–2
example endpoint design.
The following modules are included in the example design:
■
<variation name>_example_pipen1b. This module is the top level of
the example endpoint design that you use for simulation.
This module provides both PIPE and serial interfaces for the
simulation environment. This module has two debug ports named
test_out and test_in (see
monitor and control internal states of the MegaCore function.
For synthesis the top level module is <variation name>_example_top.
This module instantiates the module <variation
name>_example_pipen1b and propagates only a small sub-set of the
test ports to the external I/Os. These test ports can be used in your
design.
PCI Express Compiler Version 6.1
Virtual Channel
Traffic Class to
shows the high level block diagram of the simple DMA
Mapping
“Generate Files” on page 2–11
VC0 Tx
VC0 Rx
VC1 Tx
VC1 Rx
Appendix
PHY Support Module
(< variation name >)
PCI Express MegaCore
Function Variation
for more information.
C) which allows you to
Altera Corporation
December 2006