IPR-PCIE/8 Altera, IPR-PCIE/8 Datasheet - Page 160

• Manufacturer Part Number: IPR-PCIE/8
• Description: IP CORE Renewal Of IP-PCIE/8
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCIE/8

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Express Compiler, x8 Link Width
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Simple DMA Example Design
5–10
PCI Express Compiler User Guide
0x0C
0x10
0x14
(offset from BAR2,3)
Table 5–3. Example Design Control Registers (Part 2 of 2)
Register Byte
Address
13
12
11
10:8
7
6:5
4:0
31:15
14:12
11:9
8:4
3:1
0
31:15
14:3
2:0
Field
Bit
Sets the value of the Relaxed Ordering Attribute bit in all PCI Express request
headers generated by this DMA channel operation.
Sets the value of the No Snoop Attribute bit in all PCI Express request headers
generated by this DMA channel operation.
Reserved.
Sets the value of the Traffic Class field in all PCI Express request headers
generated by this DMA channel operation.
Reserved.
Sets the value of the Packet Format Field in all PCI Express request headers
generated by this DMA channel operation. The encoding is as follows:
Sets the value of the Type field in all PCI Express request headers generated by
this DMA channel operation. The supported encoding is:
00000b—Memory read or write
Reserved
MSI Traffic Class, when requesting an MSI. Write to this field to specify which
PCI-Express Traffic Class to send the MSI memory write packet.
Reserved
MSI Number, when requesting and MSI. Write to this field to specify which MSI
should be sent.
Reserved
Interrupt Request. If MSI is enabled in the endpoint (EP) design, then writing to
this bit sends a Message Signaled Interrupt (MSI). Otherwise, MSI is disabled
in the EP, and so a Legacy Interrupt message is sent.
Reserved.
Starting master memory block address for the DMA channel operation.
Bits 2:0 of the starting master memory block address are copied from the
starting PCI Express address.
00b—Memory read (3DW w/o data)
01b—Memory read (4DW w/o data)
10b—Memory write (3DW w/data)
11b—Memory write (4DW w/data)
PCI Express Compiler Version 6.1
Description
Altera Corporation
December 2006