IPR-PCIE/8 Altera, IPR-PCIE/8 Datasheet - Page 83

• Manufacturer Part Number: IPR-PCIE/8
• Description: IP CORE Renewal Of IP-PCIE/8
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCIE/8

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Express Compiler, x8 Link Width
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Specifications
Altera Corporation
December 2006
Transmit Interface Operation Signals
The transmit interface is established per initialized virtual channel and is
based on two independent busses, one for the descriptor phase
(tx_desc[127:0]) and one for the data phase (tx_data[63:0]).
Every transaction includes a descriptor. A descriptor is a standard
transaction layer packet header as defined by the PCI Express Base
Specification Revision 1.0a with the exception of bits 126 and 127, which
indicate the transaction layer packet group as described in the following
section. Only transaction layer packets with a normal data payload
include one or more data phases.
Transmit Data Path Signals
The MegaCore function assumes that transaction layer packets sent by
the application layer are well-formed, i.e., the MegaCore function will not
detect if the application layer sends it a malformed transaction layer
packet.
Transmit data path signals can be divided into two groups:
■
■
1
Descriptor Phase signals
Data Phase signals
PCI Express Compiler Version 6.1
In the following tables, transmit interface signal names suffixed
with 0 are for virtual channel 0. If the MegaCore function
implements additional virtual channels, there are an additional
set of signals suffixed with the virtual channel number.
PCI Express Compiler User Guide
3–45