IPR-PCIE/8 Altera, IPR-PCIE/8 Datasheet - Page 194

• Manufacturer Part Number: IPR-PCIE/8
• Description: IP CORE Renewal Of IP-PCIE/8
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCIE/8

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Express Compiler, x8 Link Width
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

BFM Procedures and Functions
5–44
PCI Express Compiler User Guide
Sample Duration The time elapsed since the start of the sampling window, the time when
Tx Packets
Tx Bytes
Tx MByte/sec
Tx Mbit/sec
Rx Packets
Rx Bytes
Rx MByte/sec
Rx Mbit/sec
Table 5–26. Sample Duration & Tx Packets Description
Label
ebfm_start_perf_sample or ebfm_disp_perf_sampl
Total number of packet headers transmitted by the Root Port BFM during the sample
window.
Total number of payload data bytes transmitted by the Root Port BFM during the sample
window. This is the number of QWORDs transferred multiplied by 8. No adjustment is made
for partial QWORDs due to packets that don't start or end on QWORD boundary.
Transmitted megabytes per second during the sample window. This is
the Sample Duration.
Transmitted megabits per second during the sample window. This is the
multiplied by 8.
Total number of packet headers received by the Root Port BFM during the sample window.
Total number of payload data bytes received by the Root Port BFM during the sample
window. This is the number of QWORDs transferred multiplied by 8. No adjustment is made
for partial QWORDs due to packets that don't start or end on QWORD boundary.
Received megabytes per second during the sample window. This is Rx Bytes divided by the
Sample Duration.
Received megabits per second during the sample window. This is the Rx MByte/sec
multiplied by 8.
Table 5–26
BFM Configuration Procedures
The following procedures are available in altpcietb_bfm_configure.
These procedures support configuration of the root port and endpoint
configuration space registers.
All VHDL arguments are subtype NATURAL and are input-only unless
specified otherwise. All Verilog HDL arguments are type INTEGER and
are input-only unless specified otherwise.
PCI Express Compiler Version 6.1
describes the information in
Description
Figure
5–5:
e was last called.
Tx
Altera Corporation
Tx
Bytes divided by
December 2006
MByte/sec