IPR-PCIE/8 Altera, IPR-PCIE/8 Datasheet - Page 195

• Manufacturer Part Number: IPR-PCIE/8
• Description: IP CORE Renewal Of IP-PCIE/8
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCIE/8

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Express Compiler, x8 Link Width
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Testbench & Example Designs
Altera Corporation
December 2006
Syntax
Arguments
Table 5–27. ebfm_cfg_rp_ep Procedure
ebfm_cfg_rp_ep(bar_table, ep_bus_num, ep_dev_num,
rp_max_rd_req_size, display_ep_config, addr_map_4GB_limit)
bar_table
ep_bus_num
ep_dev_num
rp_max_rd_req_size
display_ep_config
addr_map_4GB_limit
ebfm_cfg_rp_ep Procedure
The ebfm_cfg_rp_ep procedure configures the root port and endpoint
configuration space registers for operation. See
description the arguments for this procedure.
PCI Express Compiler Version 6.1
Address of the endpoint
memory. The
PCI Express bus number of the target device. This can be any value
greater than 0. The root port is configured to use this as it’s secondary
bus number.
PCI Express device number of the target device. This can be any
value. The endpoint is automatically assigned this value when it
receives it’s first configuration transaction.
Maximum read request size in bytes for reads issued by the root port.
This must be set to the maximum value supported by the endpoint
application layer. If the application layer only supports reads of the
Maximum Payload Size
request size will be set to the maximum payload size. Valid values for
this argument are 0, 128, 256, 512, 1024, 2048 and 4096.
When set to 1 many of the endpoint configuration space registers are
displayed after they have been initialized. This causes some
additional reads of registers that are not normally accessed during the
configuration process (such as the Device ID and Vendor ID).
When set to 1 the address map of the simulation system will be limited
to 4GB. Any 64-bit BARs will be assigned below the 4GB limit.
bar_table
bar_table
structure is populated by this routine.
, then this can be set to 0 and the read
PCI Express Compiler User Guide
structure in BFM shared
Table 5–27
for a
5–45