IPR-PCIE/8 Altera, IPR-PCIE/8 Datasheet - Page 65

• Manufacturer Part Number: IPR-PCIE/8
• Description: IP CORE Renewal Of IP-PCIE/8
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCIE/8

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Express Compiler, x8 Link Width
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Specifications
Altera Corporation
December 2006
Note to
(1)
Receiver
Overflow
Flow Control
Protocol Error
(FCPE)
Malformed TLP
Table 3–15. Errors Detected by the Transaction Layer (Part 2 of 2)
Considered optional by the PCI Express specification.
Error
Table
(1)
(1)
3–15:
Uncorrectable
(Fatal)
Uncorrectable
(Fatal)
Uncorrectable
(Fatal)
Type
Error Logging & Reporting
How the endpoint handles a particular error depends on the
configuration registers of the device.
error signaling and logging for an endpoint.
PCI Express Compiler Version 6.1
This error occurs when a component receives a transaction layer packet
that violates the FC credits allocated for this type of transaction layer
packet. In all cases the TLP is deleted internal to the MegaCore function
and is not presented to the application layer.
This error occurs when a component does not receive update flow control
credits within the 200 μs limit.
This error is caused by any of the following conditions:
●
●
●
●
●
●
●
●
The malformed TLP is deleted internal to the MegaCore function and not
presented to the application layer.
The data payload of a received transaction layer packet exceeds the
maximum payload size.
The TD field is asserted but no transaction layer packet digest exists,
or a transaction layer packet digest exists but the TD field is not
asserted.
A transaction layer packet violates a byte enable rule. The MegaCore
function checks for this violation, which is considered optional by the
PCI Express specifications.
A transaction layer packet for which the type and length fields do not
correspond with the total length of the transaction layer packet.
A transaction layer packet for which the combination of format and type
is not specified by the PCI Express specification.
A request specifies an address/length combination that causes a
memory space access to exceed a 4-KByte boundary. The MegaCore
function checks for this violation, which is considered optional by the
PCI Express specification.
Messages, such as
signaling, unlock, and
transmitted across the default traffic class.
A transaction layer packet that uses an uninitialized virtual channel.
Assert_INTx
Set_Slot_power_limit
Description
Figure 3–6
PCI Express Compiler User Guide
, power management, error
is a flowchart of device
, must be
3–27