IPR-PCIE/8 Altera, IPR-PCIE/8 Datasheet - Page 145

• Manufacturer Part Number: IPR-PCIE/8
• Description: IP CORE Renewal Of IP-PCIE/8
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCIE/8

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Express Compiler, x8 Link Width
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

External PHYs
Altera Corporation
December 2006
pcie_rstn
phystatus_ext
powerdown_ext[1:0]
refclk
pipe_txclk
rxdata0_ext[7:0]
rxdatak0_ext
rxelecidle0_ext
rxpolarity0_ext
rxstatus0_ext[1:0]
rxvalid0_ext
txcompl0_ext
txdata0_ext[7:0]
txdatak0_ext
txelecidle0_ext
rxdata1_ext[7:0]
rxdatak1_ext
rxelecidle1_ext
rxpolarity1_ext
rxstatus1_ext[1:0]
rxvalid1_ext
Table 4–3. 8-bit PHY Interface Signals (Part 1 of 2)
Signal Name
I
I
O
I
O
I
I
I
O
I
I
O
O
O
O
I
I
I
O
I
I
Direction
8-bit PHY Interface Signals
The external I/O signals for the 8-bit PIPE Interface Modes are
summarized in
whether the PHY mode has a TxClk, some of the signals may not be
available as noted.
PCI Express Reset signal, active low.
PIPE Interface Lane 0 Tx Compliance control
PIPE Interface Lane 1 Rx Data K-character flag.
PIPE Interface phystatus signal. PHY is signaling
completion of the requested operation
PIPE Interface powerdown signal, requests the
PHY to enter the specified power state.
Input clock connected to the PIPE Interface
signal from the PHY.
and data signals. Depending on whether this is an
SDR or DDR interface this clock will be either 250
MHz or 125 MHz.
Source synchronous transmit cock signal for
clocking Tx Data and Control signals going to the
PHY.
PIPE Interface Lane 0 Rx Data signals, carries the
parallel received data.
PIPE Interface Lane 0 Rx Data K-character flag.
PIPE Interface Lane 0 Rx Electrical Idle Indication. Always
PIPE Interface Lane 0 Rx Polarity Inversion Control Always
PIPE Interface Lane 0 Rx Status flags.
PIPE Interface Lane 0 Rx Valid indication
PIPE Interface Lane 0 Tx Data signals, carries the
parallel transmit data.
PIPE Interface Lane 0 Tx Data K-character flag.
PIPE Interface Lane 0 Tx Electrical Idle Control
PIPE Interface Lane 1 Rx Data signals, carries the
parallel received data.
PIPE Interface Lane 1 Rx Electrical Idle Indication. Only in x4
PIPE Interface Lane 1 Rx Polarity Inversion Control Only in x4
PIPE Interface Lane 1 Rx Status flags.
PIPE Interface Lane 1 Rx Valid indication
PCI Express Compiler Version 6.1
Table
4–3. Depending on the number of lanes selected and
Description
U
sed to clock all of the status
PCI Express Compiler User Guide
pclk
Always
Always
Always
Always
Only in modes that
have the
Always
Always
Always
Always
Always
Always
Always
Always
Only in x4
Only in x4
Only in x4
Only in x4
Availability
TxClk
4–13