IPR-PCIE/8 Altera, IPR-PCIE/8 Datasheet - Page 129

• Manufacturer Part Number: IPR-PCIE/8
• Description: IP CORE Renewal Of IP-PCIE/8
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCIE/8

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Express Compiler, x8 Link Width
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Specifications
Altera Corporation
December 2006
tx_outn
where n is
the lane
number
ranging from
0-7
rx_inn
where n is
the lane
number 0-7
pipe_mode
Table 3–39. 1-Bit Interface Signals
Signal
O
I
I
I/O
Transmit input 0. This signal is the serial output of lane 0 (2.5 Gbps on differential signals).
Receive input 0. This signal is the serial input of lane 0 (2.5 Gbps on differential signals).
pipe_mode
interface. Setting
1-bit interface. When simulating, you can set this signal to indicate which interface is used
for the simulation. When compiling your design for an Altera device, set this signal to 0.
Serial Interface Signals
Table 3–39
number 0 also exist for lanes 1 - 3, as marked in the table. These signals
are available if you use the Stratix GX PHY or the Stratix II GX PHY.
PIPE Interface Signals
The x1 and x4 MegaCore function is compliant with the 16-bit version of
the PIPE interface, enabling use of an external PHY. The x8 MegaCore
function is compliant with the 8-bit version of the PIPE interface. These
signals are available even when you select the Stratix GX PHY or
Stratix II GX PHY so that you can simulate using both the 1-bit and the
PIPE interface. Typically, simulation is much faster using the PIPE
interface. See
lanes 1-7, as marked in the table.
selects whether the MegaCore function uses the PIPE interface or the 1-bit
PCI Express Compiler Version 6.1
pipe_mode
describes the serial interface signals. Signals that include lane
Table
3–40. Signals that include lane number 0 also exist for
to a 1 selects the PIPE interface, setting it to 0 selects the
Description
PCI Express Compiler User Guide
3–91