IPR-PCIE/8 Altera, IPR-PCIE/8 Datasheet - Page 109

• Manufacturer Part Number: IPR-PCIE/8
• Description: IP CORE Renewal Of IP-PCIE/8
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCIE/8

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Express Compiler, x8 Link Width
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Specifications
Figure 3–28. Transaction with a Data Payload & Wait States Waveform
Altera Corporation
December 2006
Descriptor
Signals
Signals
Data
rx_desc[135:128]
rx_desc[127:64]
rx_data[63:32]
rx_desc[63:0]
rx_data[31:0]
rx_be[7:0]
rx_mask
rx_abort
rx_retry
rx_ack
rx_req
rx_dfr
rx_ws
Transaction with Data Payload & Wait States
The application layer can assert rx_ws as often as it likes. In
the MegaCore function receives a completion transaction of 4 DWORDS.
Bit 2 of rx_data[63:0] is set to 1. Both the application layer and the
MegaCore function insert wait states. Normally rx_data[63:0] would
contain data in clock cycle 4, but the MegaCore function has inserted a
wait state by deasserting rx_dv.
In clock cycle 11, data transmission does not resume until both of the
following conditions are met:
■
■
rx_dv
The MegaCore function asserts rx_dv at clock cycle 10, thereby
ending a MegaCore function-induced wait state.
The application layer deasserts rx_ws at clock cycle 11, thereby
ending an application interface-induced wait state.
X
X
X
1
PCI Express Compiler Version 6.1
X
X
X
2
CPLD 4DW
3
Valid
Valid
4
5
DW 0
F0h
6
Clock Cycles
DW 2
FFh
DW 1
7
8
9
X
X
PCI Express Compiler User Guide
X
X
X
10
DW 3
0Fh
11
12
13
X
X
X
14
Figure
3–28,
3–71