IPR-PCIE/8 Altera, IPR-PCIE/8 Datasheet - Page 139

• Manufacturer Part Number: IPR-PCIE/8
• Description: IP CORE Renewal Of IP-PCIE/8
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCIE/8

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Express Compiler, x8 Link Width
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

External PHYs
Figure 4–4. 8-bit DDR Mode with a Source Synchronous Transmit Clock
Altera Corporation
December 2006
External connection in user logic
clk125_out
txdata
txclk
clk125_in
pclk
rxdata
■
■
An edge detect circuit is used to detect the relationships between the 125
MHz clock and the 250 MHz rising edge to properly sequence the 16-bit
data into the 8-bit output register.
Mode 3
Q
Q
Q
Q
Edge Detect and Sync
PLL
A 250 MHz "early" clock PLL output clocks an 8-bit SDR transmit
data output register. This 250 MHz early output is multiplied from
the 125 MHz refclk and is early in relation to the refclk. A 250
MHz single data rate register for the 125 MHz DDR output allows
you to use the SDR output registers in the Cyclone II IOB.
An optional 62.5 MHz TLP Slow clock is provided for x1
implementations.
1
4
1
4
A
D
0
0
PCI Express Compiler Version 6.1
ENB
ENB
8-bit DDR Mode with txclk
DDIO
ENB
0
0
0
A
D
A
D
Q 1
Q 4
clk250_early
Q
Q
1
4
ENB
D
A
tlp_clk
PCI Express Compiler User Guide
PCIe IP MegaCore
txdata_h
txdata_l
refclk
clk125_in
tlp_clk
clk125_out
4–7