IPR-PCIE/8 Altera, IPR-PCIE/8 Datasheet - Page 166

• Manufacturer Part Number: IPR-PCIE/8
• Description: IP CORE Renewal Of IP-PCIE/8
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCIE/8

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Express Compiler, x8 Link Width
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Chaining DMA Example Design
5–16
PCI Express Compiler User Guide
32-bit BAR0
32-bit BAR1
64-bit BAR1:0
32-bit BAR2
32-bit BAR3
64-bit BAR3:2
32-bit BAR4
32-bit BAR5
64-bit BAR5:4
Expansion ROM BAR Not implemented by Example Design; behavior is unpredictable.
I/O Space BAR (any) Not implemented by Example Design; behavior is unpredictable.
Table 5–4. Example Design BAR Map
Memory BAR
Example Design BAR/Address Map
The example design maps received memory transactions to either the
target memory block or the control register block based on which BAR the
transaction matched. There are multiple BARs that map to each of these
blocks to maximize interoperability with different variation files.
Table 5–4
The example design control register block is used primarily to set up
DMA channel operations. The control register block sets the addresses,
size, and attributes of the DMA channel operation. Executing a DMA
channel operation includes the following steps:
1.
2.
3.
4.
5.
Maps to 32-KByte target memory block. Use the rc_slave module
to bypass the chaining DMA
Maps to control DMA Read and DMA write register header,
requires a minimum of 256 bytes.
Maps to 32-KByte target memory block. Use the rc_slave module
to bypass the chaining DMA
Writing the PCI Express address to the registers at offset 0x00 and
0x04.
Writing the master memory block address to the register at offset
0x14.
Writing the length of the requested operation to the register at offset
0x08.
Writing the attributes (including PCI Express memory write or read
direction) of the requested operation to the register at offset 0x0C.
Writing to this register starts the execution of the DMA channel
operation.
Reading the DMA channel operation in progress bit at offset 0x0C to
determine when the DMA channel operation has completed.
PCI Express Compiler Version 6.1
shows the mapping.
Mapping
Altera Corporation
December 2006