IPR-PCIE/8 Altera, IPR-PCIE/8 Datasheet - Page 133

• Manufacturer Part Number: IPR-PCIE/8
• Description: IP CORE Renewal Of IP-PCIE/8
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCIE/8

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Express Compiler, x8 Link Width
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

External PHY
Support
Altera Corporation
December 2006
16-bit SDR
16-bit SDR Mode (with source
synchronous transmit cock)
8-bit DDR
8-bit DDR Mode (with 8-bit DDR
source synchronous transmit cock)
8-bit SDR
8-bit SDR Mode (with Source
Synchronous Transmit Clock)
Table 4–1. External PHY Interface Modes
PHY Interface Mode
This chapter discusses external PHY support, which includes the new
external PHYs and interface modes shown in
When an external PHY is selected additional logic required to connect
directly to the external PHY is included in the <variation name> module or
entity.
The user logic must instantiate this module or entity in his design. The
implementation details for each of these modes are discussed in the
following sections.
PCI Express Compiler Version 6.1
125 MHz
125 MHz
125 MHz
125 MHz
250 MHz
250 MHz
Clock Frequency
In this generic 16-bit PIPE interface, both the
Rx
This enhancement to the generic PIPE interface
adds a
synchronously to the External PHY. The
TIXIO1100 Phy uses this mode.
This double data rate version saves I/O pins without
increasing the clock frequency. It uses a single
from the PHY for clocking data in both directions.
This double data rate version saves I/O pins without
increasing the clock frequency. A
data source synchronously in the transmit direction.
he TIXIO1100 Phy uses this mode.
This is the generic 8-bit PIPE interface. Both the
and
The Philips PX1011APHY uses this mode.
This enhancement to the generic PIPE interface
adds a
synchronously to the external PHY.
data are clocked by the
Rx
TxClk
TxClk
data are clocked by the
to clock the
to clock the
4. External PHYs
Table
Notes
TxData
TxData
pclk
4–1.
pclk
TxClk
from the PHY.
source
source
from the PHY.
clocks the
Tx
pclk
and
Tx
4–1