IPR-PCIE/8 Altera, IPR-PCIE/8 Datasheet - Page 124

• Manufacturer Part Number: IPR-PCIE/8
• Description: IP CORE Renewal Of IP-PCIE/8
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCIE/8

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Express Compiler, x8 Link Width
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Signals
Figure 3–41. MSI Interrupt Signals Waveform
3–86
PCI Express Compiler User Guide
app_msi_num[4:0]
app_msi_tc[2:0]
app_msi_ack
app_msi_req
Figure 3–41
the root port in
app_msi_req and app_msi_ack is 1 clock cycle.
Table 3–34
messages are allocated and two in which only four are allocated.
MSI generated for hot plug, power management events, and system
errors always use TC0. MSI generated by the application layer can use
any traffic class. For example, a DMA that generates an MSI at the end of
a transmission can use the same traffic control as was used to transfer
data.
System error
Hot plug and power management event
Application
Table 3–34. MSI Messages Requested, Allocated & Mapped
1
PCI Express Compiler Version 6.1
2
describes 3 example implementations; one in which all 32 MSI
illustrates the interactions among MSI interrupt signals for
3
Figure
4
MSI
Valid
Valid
5
3–40. The minimum latency possible between
6
Clock Cycles
7
8
9
10
29:0
32
31
30
11
12
Allocated
13
1:0
Altera Corporation
4
3
2
December 2006
2:0
4
3
3