IPR-PCIE/8 Altera, IPR-PCIE/8 Datasheet - Page 243

• Manufacturer Part Number: IPR-PCIE/8
• Description: IP CORE Renewal Of IP-PCIE/8
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCIE/8

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Express Compiler, x8 Link Width
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Altera Corporation
December 2006
ltssm_r
rxl0s_sm
txl0s_sm
timeout
Table C–1. test_out Signals for the x1 and x4 MegaCore Functions (Part 12 of 17)
Signal
MAC
ltssm
MAC
ltssm
MAC
ltssm
MAC
ltssm
Subblock
324:320
326:325
329:327
330
PCI Express Compiler Version 6.1
Bit
LTSSM state. LTSSM state encoding:
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
Receive L0s state. Receive L0s state machine:
●
●
●
●
TX L0s state. Transmit L0s state machine:
●
●
●
●
●
LTSSM timeout. This signal serves as a flag that indicates that
the LTSSM time-out condition has been reached for the current
LTSSM state.
00000: detect.quiet
00001: detect.active
00010: polling.active
00011: polling.compliance
00100: polling.configuration
00101: reserved (polling.speed)
00110: config.linkwidthstart
00111: config.linkaccept
01000: config:disable
01001: config.loopback.entry
01010: config.loopback.active
01011: config.loopback.exit
01100: recovery.rcvlock
01101: recovery.rcvconfig
01110: recovery.idle
01111: L0
10000: disable
10001: loopback.entry
10010: loopback.active
10011: loopback.exit
10100: hot.reset
10101: L0s (transmit only)
10110: L1.entry
10111: L1.idle
11000: L2.idle
11001: L2.transmit.wake
00: inact
01: idle
10: fts
11: out.recovery
000b: inact
001b: entry
010b: idle
011b: fts
100b: out.l0
Description
PCI Express Compiler User Guide
C–13