IPR-PCIE/8 Altera, IPR-PCIE/8 Datasheet - Page 185

• Manufacturer Part Number: IPR-PCIE/8
• Description: IP CORE Renewal Of IP-PCIE/8
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCIE/8

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Express Compiler, x8 Link Width
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Testbench & Example Designs
Altera Corporation
December 2006
Syntax
Arguments
Table 5–19. ebfm_barwr_imm Procedure
ebfm_barwr_imm(bar_table, bar_num, pcie_offset, imm_data,
byte_len, tclass)
bar_table
bar_num
pcie_offset
imm_data
byte_len
tclass
ebfm_barwr_imm Procedure
The ebfm_barwr_imm procedure writes up to four bytes of data to an
offset from the specified endpoint BAR.
PCI Express Compiler Version 6.1
Address of the endpoint
memory
Number of the BAR used with
Express address
Address offset from the BAR base
Data to be written.
In VHDL, this argument is a std_logic_vector(31 downto 0).
In Verilog HDL, this argument is reg [31:0].
In both languages, the bits written depend on the length as follows:
Length of the data to be written in bytes. Maximum length is 4 bytes.
Traffic Class to be used for the PCI Express transaction.
1
4
3
2
Length Bits Written
bar_table
pcie_offset
31 downto 0
23 downto 0
15 downto 0
PCI Express Compiler User Guide
7 downto 0
structure in BFM shared
to determine PCI
5–35