IPR-PCIE/8 Altera, IPR-PCIE/8 Datasheet - Page 157

• Manufacturer Part Number: IPR-PCIE/8
• Description: IP CORE Renewal Of IP-PCIE/8
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCIE/8

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Express Compiler, x8 Link Width
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Testbench & Example Designs
Altera Corporation
December 2006
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<variation name>.vhd or
<variation name>.v— This file instantiates the <variation name>_core
entity (or module) that is described elsewhere in this section and
includes additional logic required to support the specific PHY you
have chosen for your variation. You should include this file when
you compile your design in the Quartus II software.
<variation name>_core.v or <variation name>_core.vhd —This
variation name module is created by MegaWizard interface during
the generate phase, based on the parameters that you set when you
parameterize the MegaCore function (see
page
model produced by Quartus II software is used. The IP functional
simulation model is either the <variation name>_core.vho or
<variation name>_core.vo file. The associated <variation
name>_core.vhd or <variation name>_core.v file is used by the
Quartus II software during compilation. For information on
producing a functional simulation model, see
on page
altpcierd_example_app —This example application layer design
contains the master and slave modules. It also includes Traffic Class
(TC) to Virtual Channel (VC) mapping logic that maps requests as
specified by the mapping tables in the MegaCore functions
configuration space. For more information, see
page 3–87
altpcierd_slave —The slave module handles all memory read and
write transactions received from the PCI Express link. Depending on
which Base Address Register (BAR) the transaction matched, the
transaction is directed either to the target memory or the control
register space. For more information on the BAR and address
mapping, see
transactions received, the slave module generates the required
completion and passes it to the MegaCore function for transmission.
altpcierd_master —This is the master module that includes the
following functions:
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PCI Express Compiler Version 6.1
DMA channel that generates memory read and write
transactions on the PCI Express link.
Master memory block that can be the source of data for memory
write transactions initiated by the DMA channel and the sink of
data for memory read transactions.
2–5). For simulation purposes, the IP functional simulation
2–9.
“Example Design BAR/Address
PCI Express Compiler User Guide
“Parameterize” on
“Set Up Simulation”
Map”. For any read
Table 3–35 on
5–7