IPR-PCIE/8 Altera, IPR-PCIE/8 Datasheet - Page 188

• Manufacturer Part Number: IPR-PCIE/8
• Description: IP CORE Renewal Of IP-PCIE/8
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCIE/8

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Express Compiler, x8 Link Width
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

BFM Procedures and Functions
5–38
PCI Express Compiler User Guide
Syntax
Arguments
Table 5–22. ebfm_cfgwr_imm_wait Procedure
ebfm_cfgwr_imm_wait(bus_num, dev_num, fnc_num, imm_regb_ad, regb_ln,
imm_data, compl_status
bus_num
dev_num
fnc_num
regb_ad
regb_ln
imm_data
compl_status
ebfm_cfgwr_imm_wait Procedure
The ebfm_cfgwr_imm_wait procedure writes up to four bytes of data
to the specified configuration register. This procedure waits until the
write completion has been returned.
PCI Express bus number of the target device
PCI Express device number of the target device
Function number in the target device to be accessed
Byte-specific address of the register to be written
Length, in bytes, of the data written. Maximum length is four bytes. The
regb_ln
Data to be written.
In VHDL, this argument is a std_logic_vector(31 downto 0).
In Verilog HDL, this argument is reg [31:0].
In both languages, the bits written depend on the length:
In VHDL. this argument is a
the procedure on return.
In Verilog HDL, this argument is re [2:0].
In both languages, this argument is the completion status as specified in the
PCI Express specification:
PCI Express Compiler Version 6.1
Length
compl_status
4
3
2
1
000
001
010
100
and the
Bits Written
31 downto 0
23 downto 0
5 downto 0
7 downto 0
regb_ad
Definition
SC —Successful completion
UR —Unsupported Request
CRS —Configuration Request Retry Status
CA —Completer Abort
std_logic_vector
arguments cannot cross a DWORD boundary.
(2 downto 0) and is set by
Altera Corporation
December 2006