IPR-PCIE/8 Altera, IPR-PCIE/8 Datasheet - Page 67

• Manufacturer Part Number: IPR-PCIE/8
• Description: IP CORE Renewal Of IP-PCIE/8
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCIE/8

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Express Compiler, x8 Link Width
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Specifications
Altera Corporation
December 2006
Detected Parity Error
(status register bit 15)
Master Data Parity Error
(status register bit 8)
Table 3–16. Parity Error Conditions
Status Bit
Set when any received transaction layer packet is poisoned.
This bit is set when the command register parity enable bit is set and one of the
following conditions is true:
●
●
Data Poisoning
The MegaCore function implements data poisoning, a mechanism for
indicating that the data associated with a transaction is corrupted.
Poisoned transaction layer packets have the error/poisoned bit of the
header set to 1 and observe the following rules:
■
■
■
Poisoned transaction layer packets can also set the parity error bits in the
PCI configuration space status register. Parity errors are caused by the
conditions specified in
Poisoned packets received by the MegaCore function are passed to the
application layer. Poisoned transmit transaction layer packets are
likewise sent to the link.
Stratix GX PCI Express Compatibility
If during the PCI Express receiver detection sequence, some other PCI
Express devices cannot detect the Stratix GX receiver, the other device
remains in the LTSSM Detect state, the Stratix GX device remains in the
Compliance state, and the link is not initialized. This occurs because
Stratix GX devices do not exhibit the correct receiver impedance
characteristics when the receiver input is at electrical idle. Stratix GX
devices were designed before the PCI Express specification was
Transmission of a write request transaction layer packet with poisoned bit set.
Reception of a completion transaction layer packet with poison bit set.
Received poisoned transaction layer packets are sent to the
application layer and status bits are automatically updated in the
configuration space.
Received poisoned configuration write transaction layer packets are
not written in the configuration space.
The configuration space never generates a poisoned transaction
layer packet, i.e., the error/poisoned bit of the header is always set to
0.
PCI Express Compiler Version 6.1
Table
3–16.
Conditions
PCI Express Compiler User Guide
3–29