IPR-PCIE/8 Altera, IPR-PCIE/8 Datasheet - Page 189

• Manufacturer Part Number: IPR-PCIE/8
• Description: IP CORE Renewal Of IP-PCIE/8
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCIE/8

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Express Compiler, x8 Link Width
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Testbench & Example Designs
Altera Corporation
December 2006
Syntax
Arguments
Table 5–23. ebfm_cfgwr_imm_nowt Procedure
ebfm_cfgwr_imm_nowt(bus_num, dev_num, fnc_num, imm_regb_adr,
regb_len, imm_data)
bus_num
dev_num
fnc_num
regb_ad
regb_ln
imm_data
ebfm_cfgwr_imm_nowt Procedure
The ebfm_cfgwr_imm_nowt procedure writes up to four bytes of data
to the specified configuration register. This procedure returns as soon as
the VC interface module accepts the transaction, allowing other writes to
be issued in the interim. Use this procedure only when successful
completion status is expected.
PCI Express bus number of the target device
PCI Express device number of the target device
Function number in the target device to be accessed
Byte-specific address of the register to be written
Length, in bytes, of the data written. Maximum length is four bytes, The
the
Data to be written
In VHDL. this argument is a std_logic_vector(31 downto 0).
In Verilog HDL, this argument is reg [31:0].
In both languages, the bits written depend on the length:
Length
regb_ad
4
3
2
1
PCI Express Compiler Version 6.1
arguments cannot cross a DWORD boundary.
Bits Written
31 downto 0
23 downto 0
5 downto 0
7 downto 0
PCI Express Compiler User Guide
regb_ln
5–39