IPR-PCIE/8 Altera, IPR-PCIE/8 Datasheet - Page 111

• Manufacturer Part Number: IPR-PCIE/8
• Description: IP CORE Renewal Of IP-PCIE/8
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCIE/8

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Express Compiler, x8 Link Width
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Specifications
Altera Corporation
December 2006
Generic PIPE PHY Clocking Configuration
When you implement a generic PIPE PHY in the MegaCore function, you
must provide a 125-MHz clock on the clk125_in input. Typically, the
generic PIPE PHY provides the 125-MHz clock across the PIPE interface.
All of the function’s interfaces, including the user application interface
and the PIPE interface, are synchronous to the clk125_in input. You are
not required to use the refclk and clk125_out signals in this case. See
Figure
Figure 3–29. Generic PIPE PHY Clock Configuration
Note to
(1)
Stratix GX PHY, 100 MHz Reference Clock
If you implement a Stratix GX PHY with a 100-MHz reference clock, you
must provide a 100-MHz clock on the refclk input. Typically, this clock
is the 100-MHz PCI Express reference clock as specified by the Card
Electro-Mechanical (CEM) specification.
In this configuration, the 100-MHz refclk connects to an enhanced PLL
within the MegaCore function to create a 125-MHz clock for use by the
Stratix GX transceiver and as the clk125_out signal. The 125-MHz clock
is provided on the clk125_out signal.
You must connect clk125_out back to the clk125_in input, for
example, through a distribution circuit needed in the application. All of
the function’s interfaces, including the user application interface and the
PIPE interface, are synchronous to the clk125_in input. See
Figure
User and PIPE interface signals are synchronous to clk125_in.
from PIPE PHY
125-MHz pclk
PCI Express Compiler Version 6.1
3–29.
3–30.
Figure
3–29:
Not Required
refclk
clk125_in
altpcie_64b_x4_pipen1b: External PHY
PCI Express Compiler User Guide
clk
MegaCore Function
All Logic in
(1)
clk125_out
Not Required
3–73