IPR-PCIE/8 Altera, IPR-PCIE/8 Datasheet - Page 42

• Manufacturer Part Number: IPR-PCIE/8
• Description: IP CORE Renewal Of IP-PCIE/8
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCIE/8

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Express Compiler, x8 Link Width
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Functional Description
3–4
PCI Express Compiler User Guide
Tracing a transaction through the receive data path involves the following
steps:
1.
2.
3.
4.
5.
Tracing a transaction through the transmit data path involves the
following steps:
1.
2.
3.
4.
The transaction layer receives a transaction layer packet from the
data link layer.
The configuration space determines whether the transaction layer
packet is well formed and directs the packet to the appropriate
virtual channel based on TC/virtual channel mapping.
Within each virtual channel, transaction layer packets are stored in a
specific part of the receive buffer depending on the type of
transaction (posted, non-posted, and completion).
The transaction layer packet FIFO block stores the address of the
buffered transaction layer packet.
The receive sequencing and reordering block shuffles the order of
waiting transaction layer packets as needed, fetches the address of
the priority transaction layer packet from the transaction layer
packet FIFO block, and initiates the transfer of the transaction layer
packet to the application layer. Receive logic separates the
descriptor from the data of the transaction layer packet and
transfers them across the receive descriptor bus rx_desc[135:0],
and receive data bus rx_data[63:0] to the application layers.
The MegaCore function informs the application layer with transmit
credit tx_cred[21:0] that sufficient flow control credits exist for
a particular type of transaction. The application layer may choose to
ignore this information.
The application layer requests a transaction layer packet
transmission. The application layer must provide the PCI Express
transaction header on the tx_desc[127:0] bus and be prepared
to provide the entire data payload on the tx_data[63:0] bus in
consecutive cycles.
The MegaCore function verifies that sufficient flow control credits
exist, and acknowledges or postpones the request.
The transaction layer packet is forwarded by the application layer,
the transaction layer arbitrates among virtual channels, and then
forwards the priority transaction layer packet to the data link layer.
PCI Express Compiler Version 6.1
Altera Corporation
December 2006