IPR-PCIE/8 Altera, IPR-PCIE/8 Datasheet - Page 244

• Manufacturer Part Number: IPR-PCIE/8
• Description: IP CORE Renewal Of IP-PCIE/8
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCIE/8

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Express Compiler, x8 Link Width
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Test-Out Interface Signals for x1 and x4 MegaCore Functions
C–14
PCI Express Compiler User Guide
txos_end
tx_ack
tx_ctrl
txrx_det
tx_pad
rx_ts1
rx_ts2
Table C–1. test_out Signals for the x1 and x4 MegaCore Functions (Part 13 of 17)
Signal
MAC
ltssm
MAC
ltssm
MAC
ltssm
MAC
ltssm
MAC
ltssm
MAC
ltssm
MAC
ltssm
Subblock
331
332
335:333
343:336
351:344
359:352
367:360
PCI Express Compiler Version 6.1
Bit
Transmit LTSSM exit condition. This signal serves as a flag that
indicates that the LTSSM exit condition for the next state (to go
to L0) has been completed. If the next state is not reached in a
timely manner, it is due to a problem on the receiver.
Transmit PLP acknowledge. This signal is active for 1 clock
cycle when the requested PLP (physical layer packet) has been
sent to the link. The type of packet is defined by the
signal.
Transmit PLP type. This signal indicates the type of transmitted
PLP:
●
●
●
●
●
●
●
●
Receiver detect result. This signal serves as a per lane flag that
reports the receiver detection result. The 4 MSB are always
zero.
Force PAD on transmitted TS pattern. This is a per lane internal
signal that force PAD transmission on the link and lane field of
the transmitted TS1/TS2 OS. The MegaCore function considers
that lanes indicated by this signal should not be initialized
during the initialization process.
The 4 MSB are always zero.
Received TS1: This signal indicates that a TS1 has been
received on the specified lane. This signal is cleared when a
new state is reached by the LTSSM state machine.
The 4 MSB are always zero.
Received TS2. This signal indicates that a TS1 has been
received on the specified lane. This signal is cleared when a
new state is reached by the LTSSM state machine.
The 4 MSB are always zero.
000: Electrical Idle
001: Receiver detect during Electrical
Idle
010: TS1 OS
011: TS2 OS
100: D0.0 idle data
101: FTS OS
110: IDL OS
111: Compliance pattern
Description
Altera Corporation
December 2006
tx_ctrl