IPR-PCIE/8 Altera, IPR-PCIE/8 Datasheet - Page 5

• Manufacturer Part Number: IPR-PCIE/8
• Description: IP CORE Renewal Of IP-PCIE/8
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCIE/8

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Express Compiler, x8 Link Width
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Contents
Chapter 5. Testbench & Example Designs
Appendix A.
Configuration Signals
Appendix B.
Transaction Layer Packet Header Formats
Appendix C.
Test Port Interface Signals
Altera Corporation
December 2006
Testbench ................................................................................................................................................ 5–3
Simple DMA Example Design ............................................................................................................. 5–5
Chaining DMA Example Design ....................................................................................................... 5–11
Test Driver Modules ............................................................................................................................ 5–20
Root Port BFM ...................................................................................................................................... 5–27
BFM Procedures and Functions ......................................................................................................... 5–33
Configuration Signals for x1 and x4 MegaCore Functions ............................................................. A–1
Configuration Signals for x8 MegaCore Functions ......................................................................... A–6
Content Without Data Payload .......................................................................................................... B–1
Content with Data Payload ................................................................................................................. B–2
Test-Out Interface Signals for
x1 and x4 MegaCore Functions .......................................................................................................... C–2
Test-Out Interface Signals for x8 MegaCore Functions ................................................................ C–19
Test-In Interface .................................................................................................................................. C–22
Example Design BAR/Address Map ............................................................................................ 5–8
Example Design BAR/Address Map .......................................................................................... 5–16
Chaining DMA Descriptor Tables ............................................................................................... 5–17
BFM Test Driver Module For Simple DMA Example Design ................................................. 5–20
BFM Test Driver Module for Chaining DMA Example Design .............................................. 5–23
BFM Memory Map ......................................................................................................................... 5–29
Configuration Space Bus and Device Numbering .................................................................... 5–29
Configuration of Root Port and Endpoint .................................................................................. 5–30
Issuing Read & Write Transactions to the Application Layer ................................................. 5–32
BFM Read and Write Procedures ................................................................................................. 5–34
BFM Performance Counting ......................................................................................................... 5–41
BFM Read/Write Request Procedures ........................................................................................ 5–42
BFM Configuration Procedures ................................................................................................... 5–44
BFM Shared Memory Access Procedures ................................................................................... 5–46
BFM Log & Message Procedures ................................................................................................. 5–50
Verilog HDL Formatting Functions ............................................................................................. 5–56
Procedures and Functions Specific to the chaining DMA Design .......................................... 5–61
PCI Express Compiler Version 6.1
PCI Express Compiler User Guide
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