IPR-PCIE/8 Altera, IPR-PCIE/8 Datasheet - Page 251

• Manufacturer Part Number: IPR-PCIE/8
• Description: IP CORE Renewal Of IP-PCIE/8
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCIE/8

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Express Compiler, x8 Link Width
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Altera Corporation
December 2006
rx_8d00
rx_idl
rx_linkpad
rx_lanepad
rx_tsnum
lane_act
lane_rev
count0
count1
count2
count3
count4
count5
Table C–2. test_out Signals for the x8 MegaCore Functions (Part 3 of 4)
Signal
MAC
ltssm
MAC
ltssm
MAC
ltssm
MAC
ltssm
MAC
ltssm
MAC
ltssm
MAC
ltssm
MAC
deskew
MAC
deskew
MAC
deskew
MAC
deskew
MAC
deskew
MAC
deskew
Subblock
PCI Express Compiler Version 6.1
55:48
63:56
71:64
79:72
87:80
91:88
95:92
98:96
101:99
104:102
107:105
110:108
113:111
Bit
Received 8 D0.0 symbol: This signal indicates that eight
consecutive Idle data symbols have been received. This
signal is meaningful for config.idle and recovery.idle
states.
Received 8 D0.0 symbol: This signal indicates that eight
consecutive Idle data symbols have been received. This
signal is meaningful for config.idle and recovery.idle
states.
Received Link Pad TS: This signal indicates that the Link
field of the received TS1/
TS2 is set to PAD for the specified lane.
Received Lane Pad TS: This signal indicates that the Lane
field of the received TS1/
TS2 is set to PAD for the specified lane.
Received Consecutive Identical TSNumber: This signal
reports the number of consecutive identical TS1/TS2
which have been received with exactly the same
parameters since entering this state. When the maximum
number is reached, this signal restarts from zero. Note
that this signal corresponds to the lane configured as
logical lane 0.
Lane Active Mode: This signal indicates the number of
Lanes that have been configured during training:
Reserved
Deskew fifo count lane 0: This signal indicates the number
of Words in the deskew fifo for physical lane 0.
Deskew fifo count lane 1: This signal indicates the number
of Words in the deskew fifo for physical lane 1
Deskew fifo count lane 2: This signal indicates the number
of Words in the deskew fifo for physical lane 2.
Deskew fifo count lane 3: This signal indicates the number
of Words in the deskew fifo for physical lane 3.
Deskew fifo count lane 4: This signal indicates the number
of Words in the deskew fifo for physical lane 4.
Deskew fifo count lane 5:This signal indicates the number
of Words in the deskew fifo for physical lane 5.
0001: 1 lane
0010: 2 lanes
0100: 4 lanes
1000: 8 lanes
PCI Express Compiler User Guide
Description
.
C–21