IPR-PCIE/8 Altera, IPR-PCIE/8 Datasheet - Page 226

• Manufacturer Part Number: IPR-PCIE/8
• Description: IP CORE Renewal Of IP-PCIE/8
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCIE/8

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Express Compiler, x8 Link Width
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Configuration Signals for x8 MegaCore Functions
A–10
PCI Express Compiler User Guide
k_bar[191:160]
k_bar[223:192]
k_cnt[10:0]
k_cnt[15:11]
k_cnt[20:12]
k_cnt[23:21]
k_cnt[35:24]
k_cred0[7:0]
k_cred0[19:8]
k_cred0 [27:20]
k_cred0[35:28]
Table A–2. Configuration Signals for x8 MegaCore Functions
Signal
System: BAR
Table (BAR5)
System: BAR
Table (Exp
ROM)
Fixed to 17
Power
Management:
Idle Threshold
for L0s Entry
Fixed to 30
Fixed to 0
Fixed to 200
Calculated: VC
Table Posted
Header Credit
Calculated: VC
Table Posted
Data Credit
Calculated: VC
Table Non-
Posted Header
Credit
Fixed to 0
Value or Wizard
Page/Label
PCI Express Compiler Version 6.1
BAR5 size mask and read only fields (I/O space, memory space,
prefetchable). bit 31 - 4 = size mask, bit 3 = prefetchable, bit 2 =
64 bit, bit1 = 0, bit 0 = I/O (or bit 31 - 0 = size mask if previous 64
bit).
Expansion ROM BAR size mask. bit 31 - 11 = size mask, bit 10 -
1 = 0, bit 0 = enable.
Flow control initialization timer (number in μs). Number in cycles.
Idle threshold for L0s entry (in 256 ns steps).
Update flow control credit timer (number in μs).
Reserved.
Flow control Time-Out check (number in μs).
Receive flow control credit for VC0 posted headers.
Receive flow control credit for VC0 posted data.
Receive flow control credit for VC0 non-posted headers.
Receive flow control credit for VC0 non-posted data. The Rx
buffer always has space for the maximum 1 DWORD of data that
can be sent for non-posted writes (configuration or I/O writes).
Description
Altera Corporation
December 2006