DF71251AD50FPV Renesas Electronics America, DF71251AD50FPV Datasheet - Page 97
DF71251AD50FPV
Manufacturer Part Number
DF71251AD50FPV
Description
MCU RISC FLASH 32K 8K 64LQFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH Tinyr
Datasheet
1.DF71243N50FPV.pdf
(794 pages)
Specifications of DF71251AD50FPV
Core Processor
SH-2
Core Size
32-Bit
Speed
50MHz
Connectivity
SCI
Peripherals
POR, PWM, WDT
Number Of I /o
37
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
4 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
64-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DF71251AD50FPV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
- Current page: 97 of 794
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5.2
5.2.1
Resets have priority over any exception source. There are two types of resets: power-on resets and
manual resets. As table 5.5 shows, both types of resets initialize the internal status of the CPU. In
power-on resets, all registers of the on-chip peripheral modules are initialized; in manual resets,
they are not.
Table 5.5
5.2.2
Power-On Reset by RES Pin: When the RES pin is driven low, this LSI enters the power-on
reset state. To reliably reset this LSI, the RES pin should be kept low for at least the oscillation
settling time when applying the power or when in standby mode (when the clock is halted) or at
least 20 tcyc when the clock is operating. During the power-on reset state, CPU internal states and
all registers of on-chip peripheral modules are initialized. See appendix A, Pin States, for the
status of individual pins during power-on reset mode.
In the power-on reset state, power-on reset exception handling starts when driving the RES pin
high after driving the pin low for the given time. The CPU operates as follows:
1. The initial value (execution start address) of the program counter (PC) is fetched from the
2. The initial value of the stack pointer (SP) is fetched from the exception handling vector table.
3. The vector base register (VBR) is cleared to H'00000000 and the interrupt mask bits (I3 to I0)
Type
Power-on reset
Manual reset
exception handling vector table.
of the status register (SR) are set to H'F (B'1111).
Resets
Types of Resets
Power-On Reset
Reset Status
RES
Low
High
High
High
Conditions for Transition to
WDT
Overflow
⎯
Overflow
Not overflowed Low
Overflow
Reset State
MRES
⎯
High
High
CPU, INTC
Initialized
Initialized
Initialized
Initialized
Rev. 5.00 Mar. 06, 2009 Page 77 of 770
On-Chip
Peripheral
Module
Initialized
Initialized
Not initialized Not initialized
Not initialized Not initialized
Internal State
REJ09B0243-0500
POE, PFC,
I/O Port
Initialized
Initialized
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